Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit

Patent metadata

Field	Value
Publication number	US-9818623-B2
Application number	US-201615077480-A
Country	US
Kind code	B2
Filing date	Mar 22, 2016
Priority date	Mar 22, 2016
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

First claim

What is claimed is:

1. A method comprising:
providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack;
patterning an array of mandrels in the mandrel layer;
selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of a pattern in the pattern layer;
selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern in the pattern layer;
disposing a spacer layer over the structure, the spacer layer forming a beta trench plug in the beta trench and a gamma trench plug in the gamma trench;
anisotropically etching the spacer layer to expose portions of the beta and gamma trench plugs, and form an array of spacers disposed on sidewalls of the mandrels,
wherein the exposed portions of the beta and gamma trench plugs define the beta and gamma block mask portions of the pattern, and
wherein the spacers and mandrels define alternating beta and gamma regions extending normally through the dielectric stack, the beta region including the beta block mask portion of the pattern, the gamma region including the gamma block mask portion of the pattern, the beta region extending through the mandrels, and the gamma region extending through the portions of the etch mask layer which are absent any overlaying spacers and mandrels; and

selectively etching the structure to form the pattern in the pattern layer.

2. The method of claim 1 comprising:
etching the pattern to:
form gamma and beta line trenches in the gamma and beta regions respectively of the dielectric stack,
form a beta dielectric block across a beta line trench from the beta block mask portion of the pattern, and
form a gamma dielectric block across a gamma line trench from the gamma block mask portion of the pattern; and

disposing metal in the gamma and beta line trenches to form an array of alternating parallel gamma and beta interconnection lines;
wherein the beta dielectric block extends across a beta interconnect line without extending into a gamma interconnect line and the gamma dielectric block extends across a gamma interconnect line without extending into a beta interconnect line.

3. The method of claim 1 wherein selectively etching a beta trench entirely in a mandrel of the array comprises selectively etching a first beta trench and a parallel second beta trench entirely in the mandrel, the first and second beta trenches being separated by a distance of 100 nm or less.

4. The method of claim 1 wherein selectively etching a gamma trench entirely in the etch mask layer comprises selectively etching a first gamma trench and a parallel second gamma trench entirely in the etch mask layer, the first and second gamma trenches being separated by a distance of 100 nm or less.

5. The method of claim 1 wherein the array of mandrels have a pitch of 100 nm or less.

6. The method of claim 1 wherein the array of spacers have a pitch that is half the pitch of the array of mandrels.

7. The method of claim 1 wherein the array of spacers have a pitch that is 50 nm or less.

8. The method of claim 1 wherein the mandrel layer, etch mask layer and spacer layer are composed of different materials.

9. The method of claim 8 wherein the mandrel layer, etch mask layer and spacer layer are composed of one of a silicon nitride, an amorphous silicon and a silicon oxide.

10. The method of claim 1 comprising:
the beta region having a width equal to the mandrel width; and
the gamma region having a width equal to the distance between the mandrels minus twice the spacer width.

11. The method of claim 1 comprising:
selectively etching the structure to remove the mandrels;
selectively etching the structure to remove exposed portions of the etch mask layer; and
selectively etching the structure to remove exposed portions of the pattern layer to form the pattern.

12. The method of claim 11 wherein selectively etching the structure to remove the mandrels, selectively etching the structure to remove exposed portions of the etch mask layer and selectively etching the structure to remove exposed portions of the pattern layer comprise a single integrated etch process.

13. A method comprising:
providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack;
patterning an array of mandrels in the mandrel layer;
selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of a pattern in the pattern layer;
selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern in the pattern layer;
disposing a spacer layer over the structure, the spacer layer forming a beta trench plug in the beta trench and a gamma trench plug in the gamma trench;
anisotropically etching the spacer layer to expose the beta and gamma trench plugs, and form an array of spacers disposed on sidewalls of the mandrels, wherein:
the exposed portions of the beta and gamma trench plugs define the beta and gamma block mask portions of the pattern, and
the spacers and mandrels define alternating beta and gamma regions extending normally through the dielectric stack, wherein:
the beta region extends through the mandrels, the beta region has a width equal to the mandrel width, and the beta region includes the beta block mask portion of the pattern, and
the gamma region extends through the portions of the etch mask layer which are absent any overlaying spacers and mandrels, the gamma region has a width equal to the distance between the mandrels minus twice the spacer width, and the gamma region includes the gamma block mask portion of the pattern; and

selectively etching the structure to form the pattern in the pattern layer.

14. The method of claim 13 comprising selectively etching one of:
a first beta trench and a parallel second beta trench entirely in the mandrel, wherein the first and second beta trenches are separated by a distance of 100 nm or less; and
a first gamma trench and a parallel second gamma trench entirely in the etch mask layer, wherein the first and second gamma trenches are separated by a distance of 100 nm or less.

15. The method of claim 13 wherein the mandrel layer, the etch mask layer and the spacer layer are composed of materials that are different from each other.

16. The method of claim 13 comprising:
selectively etching the structure to remove the mandrels;
selectively etching the structure to remove exposed portions of the etch mask layer; and
selectively etching the structure to remove exposed portions of the pattern layer to form the pattern.

17. The method of claim 16 comprising:
etching the pattern to:
form gamma and beta line trenches in the gamma and beta regions respectively of the dielectric stack,
form a beta dielectric block across a beta line trench from the beta block mask portion of the pattern, and

form a gamma dielectric block across a gamma line trench from the gamma block mask portion of the pattern; and
disposing metal in the gamma and beta line trenches to form an array of alternating parallel gamma and beta interconnection lines;
wherein the beta dielectric block extends across a beta interconnect line without extending into a gamma interconnect line a

Assignees

• Globalfoundries Inc

Inventors

• Stephens Jason Eugene
• Bouche Guillaume
• Kim Byoung Youp
• Child Jr Craig Michael

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P14/61 Primary

  using masks · CPC title

• H01L21/32139

  Electricity · mapped topic