Flip-chip employing integrated cavity filter, and related components, systems, and methods

Patent metadata

Field	Value
Publication number	US-9812752-B2
Application number	US-201615218626-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Sep 14, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a semiconductor die comprising a plurality of die layers, the plurality of die layers comprising:
at least one semiconductor layer;
a plurality of interconnect layers for providing interconnections to the at least one semiconductor layer, at least one of the plurality of interconnect layers comprising:
a first transmission line configured to transmit a first electromagnetic (EM) signal through a first signal transmission aperture; and
a second transmission line configured to receive a second EM signal through a second signal transmission aperture; and

a plurality of conductive elements interconnected to at least one of the plurality of interconnect layers, the plurality of conductive elements and at least one of the plurality of die layers defining an interior resonator cavity;
the interior resonator cavity configured to receive the first EM signal from the first transmission line through the first signal transmission aperture, resonate the first EM signal to generate the second EM signal comprising a filtered EM signal of the first EM signal, and couple the second EM signal on the second transmission line through the second signal transmission aperture.

2. The IC of claim 1 , wherein the plurality of die layers further comprises an aperture layer disposed between the plurality of interconnect layers and the interior resonator cavity, the aperture layer comprising the first signal transmission aperture and the second signal transmission aperture, the aperture layer and the plurality of conductive elements defining the interior resonator cavity.

3. The IC of claim 2 , wherein the aperture layer defines an external surface of the semiconductor die, wherein the first and second signal transmission apertures are formed in the external surface of the semiconductor die.

4. The IC of claim 1 , wherein the interior resonator cavity is dimensioned to correspond to a predetermined EM frequency band, such that the interior resonator cavity is configured to resonate frequencies of the first EM signal in the predetermined EM frequency band to generate the filtered EM signal.

5. The IC of claim 4 , wherein the predetermined EM frequency band has a center frequency of sixty (60) GigaHertz (GHz).

6. The IC of claim 4 , wherein the interior resonator cavity has a substantially rectangular cross-section in a plane parallel to the plurality of interconnect layers.

7. The IC of claim 6 , wherein the substantially rectangular cross-section has a width dimension corresponding to one-half (½) of a fundamental mode of a center frequency of the predetermined EM frequency band.

8. The IC of claim 1 , wherein the plurality of conductive elements comprise a plurality of solder balls.

9. The IC of claim 1 , wherein the plurality of conductive elements are configured to interconnect with complementary contacts of an external circuit such that at least one of the plurality of die layers, the plurality of conductive elements, and at least a portion of the external circuit define a faraday cage around the interior resonator cavity.

10. The IC of claim 9 , wherein the second transmission line interconnects with at least one of the plurality of conductive elements via the plurality of interconnect layers.

11. The IC of claim 9 , wherein the first transmission line interconnects with at least one of the plurality of conductive elements via the plurality of interconnect layers.

12. The IC of claim 11 , wherein the second transmission line interconnects with at least one of the plurality of conductive elements via the plurality of interconnect layers.

13. The IC of claim 1 , wherein at least a portion of the first transmission line is adjacent to the first signal transmission aperture, and at least a portion of the second transmission line is adjacent to the second signal transmission aperture.

14. The IC of claim 1 , further comprising an inductance blocker comprising at least one inductor interconnected between the first transmission line and the second transmission line.

15. The IC of claim 14 , wherein the at least one inductor is disposed in at least one of the plurality of interconnect layers of the semiconductor die.

16. The IC of claim 14 , further comprising a capacitance blocker comprising at least one capacitor interconnected between the first transmission line and the second transmission line in parallel with the at least one inductor.

17. The IC of claim 1 , further comprising a capacitance blocker comprising at least one capacitor interconnected between the first transmission line and the second transmission line.

18. The IC of claim 17 , wherein the at least one capacitor is disposed in at least one of the plurality of interconnect layers of the semiconductor die.

19. The IC of claim 1 , wherein the semiconductor die comprises a system-on-a-chip (SoC) having a plurality of functional elements configured to interoperate in a self-contained manner.

20. The IC of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a server; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; and an automobile.

21. An integrated circuit (IC) comprising:
a semiconductor die means comprising a plurality of die layer means, the plurality of die layer means comprising:
at least one semiconductor layer means;
a plurality of interconnect layer means for providing interconnections to the at least one semiconductor layer means, at least one of the plurality of interconnect layer means comprising:
a first transmission line means configured to transmit a first electromagnetic (EM) signal through a first signal transmission aperture; and
a second transmission line means configured to receive a second EM signal through a second signal transmission aperture; and

a plurality of conductive element means interconnected to at least one of the plurality of interconnect layer means, the plurality of conductive element means and at least one of the plurality of die layer means defining an interior resonator cavity;
the interior resonator cavity configured to receive the first EM signal from the first transmission line means through the first signal transmission aperture, resonate the first EM signal to generate the second EM signal comprising a filtered EM signal of the first EM signal, and couple the second EM signal on the second transmission line means through the second signal transmission aperture.

22. A method of forming an integrated circuit (IC) chip, the method comprising:
providing at least one semiconductor layer;
disposing a plurality of interconnect layers above the at least one semiconductor layer for providing interconnections to the at least one semiconductor layer, at least one of the plurality of interconnect layers comprising:
a first transmission line configured to transmit a first electromagnetic (EM) signal through a first signal transmission aperture; and
a second transmission line configured to receive a second EM signal through

Assignees

• Qualcomm Inc

Inventors

• Lee John Jong-Hoon
• Song Young Kyu
• Jow Uei-Ming
• Choi Sangjo
• Zhang Xiaonan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/243

  for decoupling, e.g. bypass capacitors · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title