High germanium content silicon germanium fins

Patent metadata

Field	Value
Publication number	US-9812530-B2
Application number	US-201615068601-A
Country	US
Kind code	B2
Filing date	Mar 13, 2016
Priority date	Sep 5, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.

First claim

What is claimed is:

1. A finned structure comprising:
a semiconductor substrate layer;
a continuous electrically insulating layer on the substrate layer, the electrically insulating layer including a bottom surface adjoining the substrate layer and a top surface, and
a plurality of parallel germanium-containing fins on the top surface of the electrically insulating layer, the electrically insulating layer being positioned between the substrate layer and the fins and electrically insulating the fins from the substrate layer, the fins having vertical, planar side walls extending vertically from the top surface of the electrically insulating layer and, in their entireties, consisting essentially of Si 1-y Ge y where y is between 0.8-1, each of the fins having a width of eight nanometers or less.

2. The finned structure of claim 1 , wherein the electrically insulating layer comprises a silicon dioxide layer and a second layer selected from the group consisting of boron nitride, hafnium oxide and aluminum oxide, the fins adjoining the second layer.

3. The finned structure of claim 1 , wherein each of the fins has a height exceeding ten nanometers.

4. The finned structure of claim 3 , wherein fin pitch is between 25 nm and 100 nm.

5. The finned structure of claim 1 , further including a nitride cap on each fin.

6. The finned structure of claim 1 , wherein the electrically insulating layer includes an oxide layer.

7. The finned structure of claim 6 , wherein the electrically insulating layer is a bilayer including a top layer adjoining the fins and a bottom layer adjoining the top layer, the top layer having greater etch resistance than the bottom layer.

8. The finned structure of claim 1 , wherein each of the fins has the same height and width.

9. The finned structure of claim 8 , wherein the fin heights are at least twice the fin widths.

10. The finned structure of claim 9 , wherein fin pitch is between 25 nm and 100 nm.

11. The finned structure of claim 1 , wherein each of the fins has a height exceeding the critical thickness of a silicon germanium layer grown on silicon and having the composition Si 1-y Ge y where y is between 0.8-1.

12. The finned structure of claim 1 , wherein the side walls of the fins are without undercuts and vertical and planar throughout their lengths.

13. The finned structure of claim 12 , wherein the electrically insulating layer is a bilayer including a top layer adjoining the fins and a bottom layer adjoining the top layer, the top layer having greater etch resistance than the bottom layer.

14. The finned structure of claim 12 , wherein the fin heights are at least twice the fin widths.

15. The finned structure of claim 14 , wherein the electrically insulating layer includes a buried oxide layer.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Bruley John
• Hashemi Pouya
• Khakifirooz Ali
• Ott John A
• Reznicek Alexander

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H01L29/161 Primary

  Electricity · mapped topic