Variable resistance memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9812501-B2
Application number	US-201514984477-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Jan 5, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.

First claim

What is claimed is:

1. A variable resistance memory device, comprising:
a plurality of first conductive layer patterns extending in a first direction;
a plurality of second conductive layer patterns over the plurality of first conductive layer patterns, the plurality of second conductive layer patterns extending in a second direction to cross the plurality of first conductive layer patterns; and
a plurality of lower cell structures formed at intersections of the plurality of first conductive layer patterns and the plurality of second conductive layer patterns, each of the plurality of lower cell structures including a lower switching element and a lower variable resistance element,
wherein the plurality of first conductive layer patterns, the plurality of second conductive layer patterns and the plurality of lower cell structures form a plurality of pattern structures, each of the plurality of pattern structures serving as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure of the variable resistance memory device,
wherein the first dummy pattern structure is formed on at least a first edge portion in the first direction, and a second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of a lower cell structure of the first dummy pattern structure, and
wherein the second dummy pattern structure is formed on at least a second edge portion in the second direction, and a first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of a lower cell structure of the second dummy pattern structure.

2. The variable resistance memory device of claim 1 , wherein
a second conductive layer pattern of the memory cell has a first width in the first direction; and
the second conductive layer pattern of the first dummy pattern structure has a second width in the first direction, the second width being greater than the first width.

3. The variable resistance memory device of claim 2 , wherein
a lower cell structure of the memory cell has the first width in the first direction; and
the lower cell structure of the second dummy pattern structure has a third width in the first direction, the third width being greater than the first width.

4. The variable resistance memory device of claim 1 , wherein
a first conductive layer pattern of the memory cell has a first width in the second direction; and
the first conductive layer pattern of the second dummy pattern structure has a second width in the second direction, the second width being greater than the first width.

5. A variable resistance memory device, comprising:
a substrate including a cell region and a dummy region adjacent to an edge portion of the cell region;
a plurality of first conductive layer patterns extending in a first direction;
a plurality of lower cell structures on the plurality of first conductive layer patterns, each of the plurality of lower cell structures including a lower switching element and a lower variable resistance element, and each of the plurality of lower cell structures having a pillar shape; and
a plurality of second conductive layer patterns on the plurality of lower cell structures, the plurality of second conductive layer patterns extending in a second direction,
wherein the second direction crosses the first direction,
wherein the plurality of first conductive layer patterns, the plurality of second conductive layer patterns and the plurality of lower cell structures define a pattern structure on the cell region and the dummy region,
wherein a shape of at least one of a first conductive layer pattern and a second conductive layer pattern on the dummy region is different from a shape of at least one of a first conductive layer pattern and a second conductive layer pattern on the cell region, and
wherein at least one of
the first conductive layer pattern on the dummy region protrudes in the second direction from a first sidewall of a first lower cell structure on the first conductive layer pattern, and
the second conductive layer pattern on the dummy region protrudes in the first direction from a second sidewall of a second lower cell structure under the second conductive layer pattern on the dummy region.

6. The variable resistance memory device of claim 5 , wherein
the second conductive layer pattern on the dummy region is at an edge portion of the dummy region in the first direction, and the shape of the second conductive layer pattern on the dummy region is different from the shape of the second conductive layer pattern on the cell region; and
the first conductive layer pattern on the dummy region is at an edge portion of the dummy region in the second direction, and the shape of the first conductive layer pattern on the dummy region is different from the shape of the first conductive layer pattern on the cell region.

7. The variable resistance memory device of claim 5 , wherein
the second conductive layer pattern on the dummy region is at an edge portion of the dummy region in the first direction; and
a width of the second conductive layer pattern on the dummy region in the first direction is greater than a width of the second conductive layer pattern on the cell region in the first direction.

8. The variable resistance memory device of claim 5 , wherein
the first conductive layer pattern on the dummy region is at an edge portion of the dummy region in the second direction; and
a width of the first conductive layer pattern on the dummy region in the second direction is greater than a width of the first conductive layer pattern on the cell region in the second direction.

9. The variable resistance memory device of claim 5 , wherein
the second conductive layer pattern on the dummy region is at an edge portion of the dummy region in the first direction.

10. The variable resistance memory device of claim 5 , wherein
the first conductive layer pattern on the dummy region is at an edge portion of the dummy region in the second direction.

11. The variable resistance memory device of claim 5 , wherein
at least a portion of the pattern structure on the dummy region has a first stacked structure;
at least a portion of the pattern structure on the cell region has a second stacked structure; and
the first and second stacked structures are substantially the same.

12. The variable resistance memory device of claim 5 , wherein
at least a portion of the pattern structure on the dummy region has a first stacked structure;
at least a portion of the pattern structure on the cell region has a second stacked structure; and
the first and second stacked structures are different.

13. A resistive memory device, comprising:
a plurality of first conductive layer patterns extending in a first direction;
a plurality of second conductive layer patterns over the plurality of first conductive layer patterns, the plurality of second conductive layer patterns extending in a second direction to cross the plurality of first conductive layer patterns; and
a plurality of lower cell structures formed at intersections of the plurality of first conductive layer patterns and the plurality of second conductive layer patterns, each of the plurality of lower cell structures including a lower switching element and a lower variable resistance element,
wherein the plurality of first conductive layer patterns, the plurality of second conductive layer patterns and the plurality of lower cell structures form a plurality of pattern structures, each of the plurality of pattern structures serving as one of a memory cell, a first

Assignees

• Lee Jin-Woo
• Kang Youn-Seon
• Jung Seung-Jae
• Ju Hyun-Su
• Terai Masayuki
• Samsung Electronics Co Ltd

Inventors

• Lee Jin-Woo
• Kang Youn-Seon
• Jung Seung-Jae
• Ju Hyun-Su
• Terai Masayuki

Classifications

• H01L27/224

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic

• H01L27/2463 Primary

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic