Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof

Patent metadata

Field	Value
Publication number	US-9812463-B2
Application number	US-201615250185-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Mar 25, 2016
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a memory stack structure extending through the alternating stack and comprising a tunneling dielectric layer and a vertical semiconductor channel, wherein first portions of an outer sidewall of the tunneling dielectric layer contact proximal sidewalls of the insulating layers; and
charge trapping material portions located at each level of the electrically conductive layers, comprising a dielectric compound including silicon and nitrogen, and contacting second portions of the outer sidewall of the tunneling dielectric layer.

2. The three-dimensional memory device of claim 1 , wherein the charge trapping material portions are vertical portions of a continuous charge trapping material layer that extends through the alternating stack, including horizontal portions located between each vertically neighboring pair of an electrically conductive layer and an insulating layer within the alternating stack, and including additional vertical portions that contact each distal sidewall of the insulating layers.

3. The three-dimensional memory device of claim 2 , wherein the continuous charge trapping material layer comprises a continuous silicon oxynitride layer.

4. The three-dimensional memory device of claim 3 , wherein the tunneling dielectric layer comprises an ONO stack that includes at least one silicon oxide portion, a silicon nitride layer, and a silicon oxide layer that contacts the vertical semiconductor channel.

5. The three-dimensional memory device of claim 4 , wherein the at least one silicon oxide portion comprises a continuous silicon oxide layer that includes the outer sidewall of the tunneling dielectric layer and continuously extending through a plurality of layers within the alternating stack.

6. The three-dimensional memory device of claim 4 , wherein the at least one silicon oxide portion comprises a plurality of discrete silicon oxide portions that include the second portions of the outer sidewall of the tunneling dielectric layer, are located at each level of the electrically conductive layer, and do not vertically extend into levels of the insulating layers.

7. The three-dimensional memory device of claim 6 , wherein:
outer sidewalls of the silicon nitride layer within the ONO stack comprises the first portions of the outer sidewall of the tunneling dielectric layer; and
the silicon nitride layer within the ONO stack contacts inner sidewalls of each of the plurality of discrete silicon oxide portions.

8. The three-dimensional memory device of claim 3 , wherein the charge trapping material portions comprise a first silicon oxynitride material, and horizontal portions of the continuous silicon oxynitride layer comprise a second silicon oxynitride material having a lesser average nitrogen concentration than the first silicon oxynitride material.

9. The three-dimensional memory device of claim 1 , wherein the charge trapping material portions comprise discrete silicon nitride portions that are located at each level of the electrically conductive layers and do not vertically extend to levels of the insulating layers.

10. The three-dimensional memory device of claim 9 , further comprising silicon oxynitride layers that are vertically spaced from one another, wherein a subset of the silicon oxynitride layers contacts at least one of the silicon nitride portions, and includes an upper horizontal portion contacting the tunneling dielectric layer, a lower horizontal portion contacting the tunneling dielectric layer, and a vertical portion contacting a distal sidewall of the respective insulating layer.

11. The three-dimensional memory device of claim 1 , further comprising a continuous backside blocking dielectric layer extending through the alternating stack, contacting each of the charge trapping material portions, and located between each vertically neighboring pair of an insulating layer and an electrically conductive layer within the alternating stack.

12. The three-dimensional memory device of claim 1 , wherein the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layers within the alternating stack, and the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack.

13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

14. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming a memory opening through the alternating stack;
forming a silicon containing material in the memory opening;
forming a memory stack structure comprising at least one tunneling dielectric sublayer of a tunneling dielectric layer and a vertical semiconductor channel over the silicon containing material in the memory opening;
forming backside recesses by removing the sacrificial material layers selective to the silicon containing material;
at least partially converting the silicon containing material into charge trapping material portions including a dielectric compound comprising silicon and nitrogen by a nitridation process through the backside recesses; and
forming electrically conductive layers in the backside recesses.

15. The method of claim 14 , wherein:
forming the silicon containing material comprises forming annular etch stop material portions which contain silicon at each level of the sacrificial material layers around the memory opening; and
the tunneling dielectric layer further comprises at least one tunneling dielectric portion which contacts each of the charge trapping material portions.

16. The method of claim 15 , wherein

Assignees

• Sandisk Technologies Llc

Inventors

• Sharangpani Rahul
• Makala Raghuveer S
• Kanakamedala Senaka
• Zhou Fei
• Peri Somesh
• Tsutsumi Masanori
• Shukla Keerti
• IKAWA Yusuke
• Sakakibara Kiyohiko
• Takii Eisuke

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6522

  introduced into a nitride material, e.g. changing SiN to SiON · CPC title

• H10P14/6316

  Formation by nitridation, e.g. nitridation of the substrate · CPC title