Microelectronic assemblies with cavities, and methods of fabrication

Patent metadata

Field	Value
Publication number	US-9812406-B2
Application number	US-201615280175-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Jun 19, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Die ( 110 ) are attached to an interposer ( 420 ), and the interposer/die assembly is placed into a lid cavity ( 510 ). The lid ( 210 ) is attached to the top of the assembly, possibly to the encapsulant ( 474 ) at the top. The lid's legs ( 520 ) surround the cavity and extend down below the top surface of the interposer's substrate ( 420 S), possibly to the level of the bottom surface of the substrate or lower. The legs ( 520 ) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer ( 420 SW) has trenches ( 478 ) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias ( 450 ) passing through the interposer substrate. Other features are also provided.

First claim

The invention claimed is:

1. An assembly comprising:
a first structure comprising a cavity; and
a second structure attached to the first structure and comprising a first microelectronic component and one or more second microelectronic components, wherein:
the first microelectronic component comprises a first substrate, the first microelectronic component comprising first circuitry, wherein the first substrate comprises a first side and one or more first holes in the first side;
each second microelectronic component comprises one or more respective second substrates, each second microelectronic component comprising respective second circuitry, each second microelectronic component being attached to the first side of the first substrate, wherein the second circuitry of each second microelectronic component is electrically coupled to the first circuitry;
wherein each second microelectronic component is located in the cavity and at least a portion of a sidewall of the cavity is located in a corresponding first hole such that at least a portion of a sidewall of the corresponding first hole extends laterally along a straight line adjacent to at least one second microelectronic component located in said cavity, and such that said at least a portion of a sidewall of the cavity extends laterally along the portion of the corresponding first hole.

2. The assembly of claim 1 wherein the one or more first holes completely laterally surround at least one second microelectronic component.

3. The assembly of claim 1 wherein a portion of a sidewall of the cavity in one said first hole completely laterally surrounds at least one second microelectronic component.

4. The assembly of claim 1 wherein at least a portion of a sidewall of the cavity does not adhere to the second structure.

5. The assembly of claim 1 wherein the second structure adheres to one or more regions inside the cavity at a distal end from the first substrate, but not to any other region.

6. The assembly of claim 1 wherein the first circuitry comprises one or more conductive vias passing through the first substrate between a top side of the first substrate and a bottom side of the first substrate, the one or more conductive vias being electrically coupled to the second circuitry of at least one second microelectronic component.

7. The assembly of claim 1 wherein:
the assembly comprises a material separating each second microelectronic component in the cavity from a surface of the cavity; and
a CTE (coefficient of thermal expansion) of the sidewall is closer to a CTE of the first microelectronic component than to a CTE of the material.

8. The assembly of claim 1 wherein:
the assembly comprises a material separating each second microelectronic component in the cavity from a surface of the cavity; and
a CTE of the sidewall is closer to a CTE of the first substrate than to a CTE of the material.

9. The assembly of claim 1 wherein at least one second microelectronic component is attached to a surface of the cavity by a first material consisting of one or more of second materials each of which is selected from a group consisting of one or more metals, one or more metal compounds, and silicon dioxide.

10. The assembly of claim 1 wherein the first material consists of one or more metals.

11. The assembly of claim 1 wherein the first material is metal silicide.

12. The assembly of claim 1 wherein the first material is silicon dioxide.

13. An assembly comprising:
a first structure comprising a cavity; and
a module at least partially located in the cavity, the module comprising a first microelectronic component and one or more second microelectronic components;
wherein:
the first microelectronic component comprises a first substrate, the first microelectronic component comprising first circuitry comprising one or more conductive vias passing through the first substrate between a top side of the first substrate and a bottom side of the first substrate; and
each of the one or more second microelectronic components comprises one or more semiconductor integrated circuits located in the cavity and electrically coupled to one or more of the one or more conductive vias but electrically insulated from the first structure; and
the first circuitry comprises one or more contact structures exposed at the bottom of the first microelectronic component, each said contact structure having at least a portion which is not inside the cavity and which is available for direct attachment to a circuit outside of the assembly but is not directly attached to a circuit outside of the assembly.

14. The assembly of claim 13 wherein a bottom of a sidewall of the cavity is at a level below each said semiconductor integrated circuit and completely laterally surrounds each said semiconductor integrated circuit.

15. The assembly of claim 13 wherein at least a portion of a sidewall of the cavity does not adhere to the second structure.

16. The assembly of claim 13 wherein the second structure adheres to one or more regions inside the cavity at a distal end from the first substrate, but not to any other region.

17. The assembly of claim 13 wherein:
the assembly comprises a material separating each second microelectronic component from a surface of the cavity; and
a CTE (coefficient of thermal expansion) of the sidewall is closer to a CTE of the first microelectronic component than to a CTE of the material.

18. The assembly of claim 13 wherein:
the assembly comprises a material separating each second microelectronic component from a surface of the cavity; and
a CTE of the sidewall is closer to a CTE of the first substrate than to a CTE of the material.

19. The assembly of claim 13 wherein at least one second microelectronic component is attached to a surface of the cavity by a first material consisting of one or more of second materials each of which is selected from a group consisting of one or more metals, one or more metal compounds, and silicon dioxide.

20. The assembly of claim 19 wherein the material is silicon dioxide.

Assignees

• Invensas Corp

Inventors

• Shen Hong
• Wang Liang
• Katkar Rajesh
• Woychik Charles G
• Gao Guilian

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W76/18

  Insulating materials, e.g. resins, glasses or ceramics · CPC title

• H10W76/17

  characterised by their materials · CPC title