Embedded semiconductor device package and method of manufacturing thereof
US-2015380356-A1 · Dec 31, 2015 · US
US9807871B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9807871-B2 |
| Application number | US-201414912176-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 11, 2014 |
| Priority date | Aug 28, 2013 |
| Publication date | Oct 31, 2017 |
| Grant date | Oct 31, 2017 |
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An electronic assembly includes a substrate having in a first zone a low contrast first conductive pattern; a high contrast fiducial mark in a second zone of the substrate different from the first zone, wherein the fiducial mark and the first conductive pattern are in registration; and a second conductive pattern aligned with the first conductive pattern.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: forming a resist layer overlying a patterned conductive nanowire layer in a first zone on a substrate to form a low contrast first conductive pattern; forming, substantially simultaneously with the first conductive pattern, a high contrast fiducial mark in a second zone of the substrate different from the first zone, wherein the fiducial mark is in registration with the first conductive pattern; forming, using the fiducial mark as a guide, a second pattern aligned with the first conductive pattern. 2. The method of claim 1 , wherein the first conductive pattern has an optical transmission of greater than about 80% optionally wherein the fiducial mark has an optical transmission of about 0% to about 50%. 3. The method of claim 1 , wherein the error in registration between the fiducial mark and the first conductive pattern is less than about 20 microns. 4. The method of claim 1 , wherein the first conductive pattern includes features having a dimension less than 200 microns in size. 5. The method of claim 1 , wherein the second pattern is conductive. 6. The method of claim 5 , wherein the second pattern is aligned with the first conductive pattern and forms an electronic assembly. 7. The method of claim 5 , wherein the patterned conductive nanowire layer in the first zone on the substrate is produced by: coating a substrate with a conductive layer comprising nanowires; applying a pattern on the conductive layer with a resist matrix material to generate on the substrate one or more first regions of exposed conductive layer and one or more second regions of resist matrix material; hardening or curing the resist matrix material; over coating the pattern with a strippable polymer layer; hardening or curing the strippable polymer layer; peeling the strippable polymer layer from the substrate; and removing the exposed conductive layer from the substrate in the one or more first regions of the substrate to form a patterned conductive layer on the substrate, wherein the patterned conductive layer comprises nanowires overlain by the resist matrix material. 8. The method of claim 7 , wherein the pattern on the conductive layer is applied by a process selected from at least one of photolithography, flexographic printing, gravure printing, ink jet printing, screen printing, spray coating, needle coating, photolithographic patterning, and offset printing. 9. An electronic assembly, comprising: a substrate comprising in a first zone a low contrast first conductive pattern; a high contrast fiducial mark in a second zone of the substrate different from the first zone; wherein the fiducial mark and the first conductive pattern are in registration; and a second conductive pattern aligned with the first conductive pattern. 10. The electronic assembly of claim 9 , wherein the fiducial mark and the first conductive pattern are in registration with a dimensional accuracy of less than about 100 microns. 11. The electronic assembly of claim 9 , wherein the fiducial mark and the first conductive pattern are in registration with a dimensional accuracy of less than about 20 microns. 12. The electronic assembly of claim 9 , wherein the difference in optical transmission in the visible light region on the substrate between the fiducial mark and the second conductive pattern is greater than about 50%. 13. The electronic assembly of claim 9 , wherein the first conductive pattern has an optical transmission in the visible light region of about 80% to about 99.9%. 14. The electronic assembly of claim 9 , wherein the fiducial mark has an optical transmission in the visible region of less than about 50%. 15. The electronic assembly of claim 9 , wherein the second conductive pattern is a circuit interconnect. 16. The electronic assembly of clam 9 , wherein the circuit interconnect is in-plane with respect to the first conductive pattern. 17. An electronic assembly, comprising: a substrate comprising in a first zone a first conductive pattern, wherein the first conductive pattern comprises conductive nanowires overlain by a layer of a resist matrix material, and wherein the conductive pattern has an optical transmission in the visible region of greater than about 80%; a fiducial mark in a second zone of the substrate different from the first zone, wherein the fiducial mark has an optical transmission in the visible region of less than about 50%, and wherein the fiducial mark and the second conductive pattern are in registration with a dimensional accuracy of less than about 100 microns; and a second conductive pattern aligned with the first conductive pattern. 18. The electronic assembly of claim 17 , wherein the resist matrix material has a thickness of about 10 nanometers to about 3000 nanometers. 19. The electronic assembly of claim 17 , wherein the resist matrix material has a light transmission of at least 80%. 20. The electronic assembly of claim 17 , wherein the second conductive pattern is a circuit interconnect.
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