Method for producing a circuit board consisting of a plurality of circuit board areas and circuit board

Patent metadata

Field	Value
Publication number	US-9226390-B2
Application number	US-201113822648-A
Country	US
Kind code	B2
Filing date	Sep 14, 2011
Priority date	Sep 17, 2010
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

For a method for producing a circuit board consisting of a plurality of circuit board areas, wherein the individual circuit board areas comprise at least one layer made of an in insulating base material and a conducting pattern located on or in the base material, the following is provided: a substrate material, at least one registration mark formed in the substrate material, a first circuit board area arranged on the substrate material, at least one additional circuit board area, which substantially adjoins the first circuit board area or at least partially overlaps the first circuit board, the additional circuit board areas being oriented relative to the registration mark, and a plurality of connections of the conducting patterns of the first circuit board area and of the at least one additional circuit board area. Thus improved registration and orientation can be achieved when circuit board areas are coupled.

First claim

The invention claimed is:

1. A method for producing a circuit board consisting of a plurality of circuit board areas, wherein individual circuit board areas comprise at least one layer made of an insulating base material and a conducting or conductive pattern located on or in the base material, said method comprising the steps of:
providing a substrate material, said substrate material comprises of a conductive material,
forming at least one registration mark in the substrate material,
arranging a first circuit board area on the substrate material while orienting the first circuit board area relative to the at least one registration mark,
connecting the conducting or conductive pattern of the first circuit board area to the conducting or conductive pattern of at least one further circuit board area,
arranging at least one additional circuit board area adjoining and at least partially overlapping the first circuit board area on a same or common surface of the substrate material where the first circuit board area is arranged while orienting the at least one additional circuit board area relative to the at least one registration mark,
wherein the first circuit board area is comprised of a flexible circuit board area,
and the at least one additional circuit board area is comprised of a rigid circuit board area;
wherein, after having connected the conducting patterns of the individual circuit board areas, the substrate material is at least partially removed in a region of the first circuit board area.

2. The method according to claim 1 , wherein at least the first circuit board area is fixed to the substrate material via an interposed adhesive.

3. The method according to claim 1 , wherein at least one electronic component is additionally arranged on the substrate material, and/or embedded in the at last one further circuit board area, and contacted with at least one conducting or conductive pattern, wherein the component is oriented relative to the at least one registration mark.

4. The method according to claim 1 , wherein the substrate material is formed by a conducting film.

5. The method according to claim 1 , wherein additional layers or plies of a multilayer circuit board are arranged on the circuit board areas disposed on the substrate material and having identical heights after connecting or pressing.

Assignees

• Haslebner Nikolai
• Leitgeb Markus
• Gossler Michael
• Morianz Mike
• Austria Tech & System Tech

Inventors

• Haslebner Nikolai
• Leitgeb Markus
• Gossler Michael
• Morianz Mike

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• Y10T29/49126

  Assembling bases · CPC title

• H05K2201/0355

  Metal foils · CPC title

• H05K3/4688 Primary

  Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602) · CPC title

• H05K1/0266 Primary

  Marks, test patterns or identification means · CPC title