Three dimensional nand flash with self-aligned select gate
US-2016307914-A1 · Oct 20, 2016 · US
Semiconductor memory device
US9806091B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9806091-B2 |
| Application number | US-201615271385-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 21, 2016 |
| Priority date | Mar 18, 2016 |
| Publication date | Oct 31, 2017 |
| Grant date | Oct 31, 2017 |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The semiconductor layer comprises: a first portion extending in the first direction and facing a plurality of the control gate electrodes; and a second portion provided on a closer side to the substrate than this first portion. A film thickness of the first portion in the second direction is larger than a film thickness of the second portion in the second direction. A crystal grain included in the first portion is larger than a crystal grain included in the second portion.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device, comprising: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a first semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the first semiconductor layer, the first semiconductor layer comprising: a first portion extending in the first direction and facing the control gate electrode; and a second portion provided on a closer side to the substrate than the first portion, a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, and a crystal grain included in the first portion being larger than a crystal grain included in the second portion. 2. The semiconductor memory device according to claim 1 , wherein the first portion includes a crystal grain larger than a film thickness of the first portion in the second direction. 3. The semiconductor memory device according to claim 1 , wherein the crystal grain included in the first portion is larger than a film thickness of the first portion in the second portion, and the crystal grain included in the second portion is smaller than a film thickness of the second portion in the second portion. 4. The semiconductor memory device according to claim 1 , further comprising a second semiconductor layer connected to an end of the first semiconductor layer on a side of the substrate. 5. The semiconductor memory device according to claim 1 , wherein the first semiconductor layer further comprises a third portion provided between the first portion and the second portion, and the third portion includes a metal atom. 6. The semiconductor memory device according to claim 5 , wherein the third portion includes a silicide. 7. The semiconductor memory device according to claim 1 , wherein the gate insulating layer includes a charge accumulation part. 8. A semiconductor memory device, comprising: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a first semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the first semiconductor layer, the first semiconductor layer comprising: a first portion extending in the first direction and facing the control gate electrode; and a second portion provided on a closer side to the substrate than the first portion, a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, the first portion including a crystal grain larger than the film thickness of the first portion in the second direction, and the second portion including a monocrystal. 9. The semiconductor memory device according to claim 8 , further comprising a second semiconductor layer connected to an end of the first semiconductor layer on a side of the substrate. 10. The semiconductor memory device according to claim 9 , wherein the second semiconductor layer includes a monocrystal, and the monocrystal included in the second portion of the first semiconductor layer has an orientation plane aligned with that of the monocrystal included in the second semiconductor layer. 11. The semiconductor memory device according to claim 8 , wherein the first semiconductor layer further comprises a third portion provided between the first portion and the second portion, and the third portion includes a metal atom. 12. The semiconductor memory device according to claim 11 , wherein the third portion includes a silicide. 13. The semiconductor memory device according to claim 8 , wherein the gate insulating layer includes a charge accumulation part. 14. A semiconductor memory device, comprising: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer, the semiconductor layer comprising: a first portion extending in the first direction and facing the control gate electrode; a second portion provided on a closer side to the substrate than the first portion; and a third portion provided between the first portion and the second portion, a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, and the third portion including a metal atom of nickel (Ni), cobalt (Co), aluminum (Al), or palladium (Pd). 15. The semiconductor memory device according to claim 14 , wherein the third portion includes a silicide. 16. The semiconductor memory device according to claim 14 , wherein the gate insulating layer includes a charge accumulation part.
Assignees
Inventors
Classifications
based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title
Cross-sectional shapes or dispositions of interconnections · CPC title
Electricity · mapped topic
- H01L27/11556Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9806091B2 cover?
- A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between th…
- Who is the assignee on this patent?
- Toshiba Memory Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L27/11556. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).