Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9070589-B2
Application number	US-201314018543-A
Country	US
Kind code	B2
Filing date	Sep 5, 2013
Priority date	Mar 6, 2013
Publication date	Jun 30, 2015
Grant date	Jun 30, 2015

Abstract

According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a semiconductor substrate;
a first layer formed above the semiconductor substrate;
a first conductive layer, an inter electrode insulating layer, and a second conductive layer sequentially stacked above the first layer;
a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter electrode insulating layer, and the second conductive layer and extending in a stacking direction;
a semiconductor layer formed on the memory film in the pair of through holes and partially crystallized; and
a metal layer filled in a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer, and the metal layer separating a first portion of the semiconductor layer in one of the pair of through holes and a second portion of the semiconductor layer in the other of the pair of through holes.

2. The device according to claim 1 , wherein the metal layer is formed on an inner surface of the connection hole.

3. The device according to claim 2 , wherein the first layer includes an insulating layer and a transistor is not formed in the first layer.

4. The device according to claim 2 , wherein the first layer includes an insulating layer of one of silicon oxide, silicon nitride, and a high k material.

5. The device according to claim 1 , wherein
the memory film is formed on an inner surface of the connection hole,
the semiconductor layer is formed on the memory film in the connection hole, and
the metal layer is in contact with the semiconductor layer in the connection hole.

6. The device according to claim 1 , wherein the metal layer contains one of Ni, Co, Al, and Pd.

7. The device according to claim 1 , wherein the metal layer contains a silicide.

8. The device according to claim 1 , wherein the first conductive layer includes a dummy gate.

9. The device according to claim 1 , wherein the semiconductor layer contains a silicide.

10. The device according to claim 1 , wherein the first layer is not connected to a control circuit.

11. The device claim 1 , further comprising
a first insulating layer formed above the second conductive layer,
wherein the semiconductor layer contains a silicide at a potion in contact with the first insulating layer.

12. The device claim 11 , wherein the silicide includes Si and a material of the metal layer.

13. The device claim 12 , wherein a material of the semiconductor layer is Si and the material of the metal layer is Ni.

14. The device claim 1 , wherein the semiconductor layer includes a single crystal or a polycrystal having a large crystal grain.

15. A nonvolatile semiconductor memory device, comprising:
a semiconductor substrate;
a first layer formed above the semiconductor substrate;
a first conductive layer, an inter electrode insulating layer, and a second conductive layer sequentially stacked above the first layer;
a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter electrode insulating layer, and the second conductive layer and extending in a stacking direction;
a semiconductor layer formed on the memory film in the pair of through holes; and
a metal layer filled in a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer, and the metal layer separating a first portion of the semiconductor layer in one of the pair of through holes and a second portion of the semiconductor layer in the other of the pair of through holes.

16. The device according to claim 15 , wherein the metal layer is formed on an inner surface of the connection hole.

17. The device according to claim 16 , wherein the first layer includes an insulating layer and a transistor is not formed in the first layer.

18. The device according to claim 16 , wherein the first layer includes an insulating layer of one of silicon oxide, silicon nitride, and a high k material.

19. The device according to claim 15 , wherein
the memory film is formed on an inner surface of the connection hole,
the semiconductor layer is formed on the memory film in the connection hole, and
the metal layer is in contact with the semiconductor layer in the connection hole.

20. The device according to claim 15 , wherein the metal layer contains one of Ni, Co, Al, and Pd.

21. The device according to claim 15 , wherein the metal layer contains a silicide.

22. The device according to claim 15 , wherein the first conductive layer includes a dummy gate.

23. The device according to claim 15 , wherein the semiconductor layer contains a silicide.

24. The device according to claim 15 , wherein the first layer is not connected to a control circuit.

25. The device claim 15 , further comprising
a first insulating layer formed above the second conductive layer,
wherein the semiconductor layer contains a silicide at a potion in contact with the first insulating layer.

26. The device claim 25 , wherein the silicide includes Si and a material of the metal layer.

27. The device claim 26 , wherein a material of the semiconductor layer is Si and the material of the metal layer is Ni.

28. The device claim 15 , wherein the semiconductor layer includes a single crystal or a polycrystal having a large crystal grain.

Assignees

• Toshiba Kk

Inventors

• Kawai Tomoya
• Fujiki Jun
• Fukuzumi Yoshiaki
• Aochi Hideaki

Classifications

• H01L27/11578 Primary

  Electricity · mapped topic

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title