Method and apparatus to increase dynamic range in delta-sigma ADC using internal feedback across all integrators in loop-filter

Patent metadata

Field	Value
Publication number	US-9800260-B1
Application number	US-201615343674-A
Country	US
Kind code	B1
Filing date	Nov 4, 2016
Priority date	Nov 4, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.

First claim

What is claimed is:

1. An apparatus comprising:
a delta-sigma analog-to-digital converter (ADC) including:
a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC;
a main quantizer circuit including a main ADC circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and
a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC; and

baseband circuitry operatively coupled to the first feedback circuit path and configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.

2. The apparatus of claim 1 , wherein the first feedback circuit path includes a first feedback quantizer circuit configured to quantize the output of the first integrator stage, and the first feedback circuit path subtracts a quantized output of the first integrator stage from the input of the sigma-delta ADC when activated.

3. The apparatus of claim 2 , wherein the first feedback quantizer circuit includes a sub-ADC circuit, and the output of the first integrator stage is operatively coupled to the input of the sub-ADC circuit.

4. The apparatus of claim 2 , including a first feed forward circuit path operatively coupled to the first feedback quantizer and a summing circuit node at the output of the delta-sigma ADC circuit, wherein the first feed forward circuit path is configured to add the quantized output of the first integrator stage to the output using the circuit summing node when the first feedback circuit path is activated.

5. The apparatus of claim 1 , including a second integrator stage operatively coupled to the output of the first integrator stage; and a second feedback circuit path operatively coupled from the output of the second integrator stage to the input of the second integrator stage, wherein the second feedback circuit path is configured to subtract an output voltage of the second integrator stage from the input of the second integrator stage, and wherein the baseband circuitry is configured to activate the second feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.

6. The apparatus of claim 5 , wherein the second feedback circuit path includes a second feedback quantizer circuit and the second feedback circuit path is configured to subtract a quantized output of the second integrator stage from the input of the second integrator stage when activated.

7. The apparatus of claim 6 , including a second feed forward circuit path operatively coupled to the second feedback quantizer and a summing circuit node at the output of the delta-sigma ADC circuit, wherein the second feed forward circuit path is configured to add the quantized output of the second integrator stage to the output using the circuit summing node when the second feedback circuit path is activated.

8. The apparatus of claim 1 , wherein the baseband circuitry is configured to detect when a signal to noise plus distortion ratio (SNDR) is less than a specified SNDR threshold, and activate the first feedback circuit path in response to the detection.

9. The apparatus of claim 1 , wherein the baseband circuitry is configured to detect when a bit error rate of the receiver chain is greater than a threshold bit error rate, and activate the first feedback circuit path in response to the detection.

10. The apparatus of claim 1 , wherein the plurality of integrator stages are included in a loop filter circuit of the delta-sigma ADC and the first feedback circuit path is configured to subtract the output voltage of the first integrator stage of the loop filter circuit from the input of the sigma-delta ADC when activated.

11. The apparatus of claim 1 , wherein the delta-sigma ADC circuit is a one-bit delta-sigma ADC circuit.

12. A method of controlling operation of a delta-sigma analog-to-digital converter (ADC), the method comprising:
receiving an input voltage at an input of the delta-sigma ADC, wherein the delta-sigma ADC includes a plurality of integrator stages including a first integrator stage;
detecting when the input voltage increases to cause distortion in the delta-sigma ADC; and
subtracting an output voltage of the first integrator stage from the input of the delta-sigma ADC in response to the detecting when the input voltage increases to cause distortion.

13. The method of claim 12 , wherein the subtracting the output voltage of the first integrator stage from the input of the delta-sigma ADC includes quantizing the output of the first integrator stage and subtracting the quantized output from the input of the sigma-delta ADC.

14. The method of claim 13 , including adding the quantized output voltage of the first integrator stage to the output of the sigma-delta ADC circuit.

15. The method of claim 12 , including:
receiving the output voltage of the first integrator stage at an input to a second integrator stage of the plurality of integrator stages; and
subtracting an output voltage of the second integrator stage from the input of the second integrator stage in response to the detecting when the input voltage increases to cause distortion.

16. The method of claim 15 , wherein the subtracting the output voltage of the second integrator stage includes quantizing the output of the second integrator stage and subtracting the quantized output from the input of the second integrator.

17. The method of claim 16 , including adding the quantized output voltage of the second integrator stage to the output of the sigma-delta ADC circuit.

18. The method of claim 12 , wherein the detecting when the input voltage increases to cause distortion in the delta-sigma ADC includes detecting when a signal to noise plus distortion ratio (SNDR) is less than a specified SNDR threshold.

19. The method of claim 12 , wherein the detecting when the input voltage increases to cause distortion in the delta-sigma ADC includes detecting when bit error rate of the receiver chain is greater than a threshold bit error rate value.

20. The method of claim 12 , wherein the plurality of integrator stages are included in a loop filter circuit of the delta-sigma ADC and wherein the subtracting the output voltage of the first integrator stage includes subtracting the output voltage of the first integrator stage of the loop filter circuit from the input of the sigma-delta ADC.

21. A wireless communication device comprising:
a radio frequency (RF) transceiver circuit;
a delta-sigma analog-to-digital converter (ADC) including:
a loop filter circuit including a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC;
a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the loop filter circuit; and
a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC; and

Assignees

• Analog Devices Global

Inventors

• Banerjee Debopam

Classifications

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H04B1/38

  Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving · CPC title

• H03M3/412 Primary

  characterised by the number of quantisers and their type and resolution · CPC title

• H04B1/0017 Primary

  Digital filtering (H04B1/001 takes precedence; digital filters per se H03H17/00) · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title