Structure of Fin Feature and Method of Making Same
US-2016071846-A1 · Mar 10, 2016 · US
Semiconductor device and method for fabricating the same
US9799769B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9799769-B2 |
| Application number | US-201715399755-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 6, 2017 |
| Priority date | Oct 8, 2015 |
| Publication date | Oct 24, 2017 |
| Grant date | Oct 24, 2017 |
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Abstract
Official abstract text for this publication.
A semiconductor device includes: a substrate having a first fin-shaped structure and a second fin-shaped structure thereon, a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure, a gate isolation directly on the second fin-shaped structure, and a gate line on the STI and the first fin-shaped structure. Preferably, the gate line includes a L-shaped structure.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a substrate having a fin-shaped structure and a second fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure and the second fin-shaped structure; a gate isolation directly on the second fin-shaped structure; a gate line on the STI and the first fin-shaped structure, wherein the gate line between the first fin-shaped structure and the gate isolation comprises a L-shaped structure; and an interlayer dielectric (ILD) layer adjacent to the gate isolation, wherein the gate line comprises a high-k dielectric layer, a work function metal layer on the high-k dielectric layer, and a low resistance metal layer on the work function metal layer, the high-k dielectric layer and the work function metal layer are buried under the low resistance metal layer of the gate line when viewed under top view, and a top surface and a bottom surface of the gate isolation, the ILD layer and the gate line are coplanar, respectively. 2. The semiconductor device of claim 1 , wherein the gate isolation and the ILD layer comprise different material. 3. The semiconductor device of claim 1 , wherein the L-shaped structure comprises a vertical portion and a horizontal portion. 4. The semiconductor device of claim 3 , wherein the vertical portion contacts the fin-shaped structure and the horizontal portion contacts the gate isolation and the STI.
Assignees
Inventors
Classifications
of inorganic materials · CPC title
by physical means only · CPC title
of conductive or resistive materials · CPC title
- H10D30/62Primary
Fin field-effect transistors [FinFET] · CPC title
of fin field-effect transistors [FinFET] · CPC title
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Frequently asked questions
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- What does patent US9799769B2 cover?
- A semiconductor device includes: a substrate having a first fin-shaped structure and a second fin-shaped structure thereon, a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure, a gate isolation directly on the second fin-shaped structure, and a gate line on the STI and the first fin-shaped structure. Preferably, the gate line includes a L-s…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D30/62. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).