Selective sputtering with light mass ions to sharpen sidewall of subtractively patterned conductive metal layer

Patent metadata

Field	Value
Publication number	US-9799519-B1
Application number	US-201615192196-A
Country	US
Kind code	B1
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A dielectric layer is formed on a silicon substrate. A liner layer is formed on the dielectric layer. A conductive metal layer is formed on the liner layer. A first sputter etching operation is performed on the conductive metal layer, wherein the first sputter etching operation uses a first type of etch chemistry configured to subtractively pattern the conductive metal layer for a first etching time period resulting in the remaining conductive metal layer having respective sidewalls that are not substantially vertical. A second sputter etching operation is performed on the remaining conductive metal layer, wherein the second sputter etching operation uses a second type of etch chemistry configured to further subtractively pattern the remaining conductive metal layer for a second etching time period resulting in the remaining conductive metal layer having respective sidewalls that are substantially vertical. The conductive metal layer remaining after the second sputter etching operation comprises a metal interconnect.

First claim

What is claimed is:

1. A method for forming a metal interconnect in a semiconductor structure, comprising:
forming a dielectric layer on a silicon substrate;
forming a liner layer on the dielectric layer;
forming a conductive metal layer on the liner layer;
performing a first sputter etching operation on the conductive metal layer, wherein the first sputter etching operation uses a first type of etch chemistry configured to subtractively pattern the conductive metal layer for a first etching time period resulting in the remaining conductive metal layer having respective sidewalls that are not substantially vertical; and
performing a second sputter etching operation on the remaining conductive metal layer, wherein the second sputter etching operation uses a second type of etch chemistry configured to further subtractively pattern the remaining conductive metal layer for a second etching time period resulting in the remaining conductive metal layer having respective sidewalls that are substantially vertical;
wherein the conductive metal layer remaining after the second sputter etching operation comprises the metal interconnect.

2. The method of claim 1 , wherein the first type of etch chemistry of the first sputter etching operation comprises argon plasma.

3. The method of claim 1 , wherein the first type of etch chemistry of the first sputter etching operation comprises one of a C—H—O, C—H, and NH 3 containing plasma.

4. The method of claim 1 , wherein the second type of etch chemistry of the second sputter etching operation comprises a light mass ion based etch chemistry.

5. The method of claim 4 , wherein the light mass ion based etch chemistry comprises one of a light mass ion plasma and a light mass ion beam.

6. The method of claim 4 , wherein the light mass ion etch is applied at an ion energy level that is selective with respect to a given material of the liner layer and a hard mask layer formed above the conductive metal layer.

7. The method of claim 5 , wherein the light mass ion plasma comprises helium plasma.

8. The method of claim 5 , wherein the light mass ion plasma comprises hydrogen plasma.

9. The method of claim 1 , wherein the conductive metal layer comprises a material selected from a group including: copper, silver, gold, cobalt, iridium, or platinum.

10. The method of claim 1 , wherein the liner layer comprises a material selected from a group including: titanium, titanium nitride, ruthenium, tungsten, iridium, gold, platinum, tantalum, tantalum nitride, cobalt, manganese, a manganese oxide, or a manganese silicate.

11. The method of claim 1 , further comprising forming a protective layer on the conductive metal layer prior to the first sputter etching operation.

12. The method of claim 11 , further comprising forming a first mask layer on the protective layer.

13. The method of claim 12 , further comprising forming a second mask layer on the first mask layer.

14. The method of claim 13 , further comprising forming an organic underlayer on the second mask layer.

15. The method of claim 14 , further comprising forming a resist layer on the organic underlayer.

16. The method of claim 15 , further comprising performing one or more removal operations on the protective layer, the first mask layer, the second mask layer, the organic underlayer and the resist layer prior to the first sputter etching operation such that the semiconductor structure comprises a remaining part of the first mask layer and a remaining part of the protective layer prior to the first sputter etching operation.

17. The method of claim 16 , further comprising:
forming another liner layer on the remaining first mask layer, the remaining protective layer, the remaining conductive metal layer, and the liner layer after the second sputter etching operation;
forming another mask layer on the other liner layer; and
removing the first mask layer, part of the other mask layer, part of the liner layer; and
part of the other liner layer.

18. The method of claim 17 , further comprising forming a dielectric layer over the remaining semiconductor structure.

Assignees

• IBM

Inventors

• Joseph Eric A
• Miyazoe Hiroyuki

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0523

  by irradiating with ultraviolet or particle radiation · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title