Semiconductor device

Patent metadata

Field	Value
Publication number	US-9799290-B2
Application number	US-201514978390-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	May 31, 2012
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A highly reliable semiconductor device that includes a transistor including an oxide semiconductor, which can display a high-definition image and can be manufactured with a high yield. The semiconductor device includes a pixel portion including a plurality of pixels, a gate signal line driver circuit portion, and a source signal line driver circuit portion including a first circuit that controls timing of sampling video signals and a second circuit that samples the video signals in accordance with the timing and then inputs the sampled video signals to the pixels. The second circuit includes a plurality of transistors in each of which an oxide semiconductor stacked layer is used as a channel formation region, the first circuit and the second circuit are electrically connected to each other by a wiring, and the wiring is electrically connected to gates of at least two transistors of the plurality of transistors.

First claim

What is claimed is:

1. A semiconductor device comprising:
a pixel portion; and
a circuit in a peripheral part of the pixel portion, comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor; and
a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring and a sixth wiring,

wherein the first wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,
wherein the second wiring is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor,
wherein the third wiring is electrically connected to a gate of the first transistor and a gate of the third transistor,
wherein the fourth wiring is electrically connected to a gate of the second transistor and a gate of the fourth transistor,
wherein the fifth wiring is electrically connected to the other of the source and the drain of the first transistor,
wherein the sixth wiring is electrically connected to the other of the source and the drain of the third transistor,
wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor comprises an oxide semiconductor layer,
wherein a first video signal is supplied to the first wiring,
wherein a second video signal is supplied to the second wiring,
wherein the oxide semiconductor layer comprises a first oxide semiconductor film and a second oxide semiconductor film which are stacked with each other,
wherein the first oxide semiconductor film comprises indium and a Group 13 element other than the indium and has a composition where an atomic percent of the indium is greater than an atomic percent of the Group 13 element other than the indium, and
wherein the second oxide semiconductor film comprises indium and a Group 13 element other than the indium and has a composition where an atomic percent of the indium is less than or equal to an atomic percent of the Group 13 element other than the indium.

2. The semiconductor device according to claim 1 , wherein the first oxide semiconductor film has a composition where the atomic percent of the indium is greater than twice of the atomic percent of the Group 13 element other than the indium.

3. The semiconductor device according to claim 1 , wherein the Group 13 element other than the indium is gallium.

4. The semiconductor device according to claim 1 , wherein the first oxide semiconductor film comprises zinc and has a composition where an atomic ratio of indium, gallium, and zinc is substantially 3:1:2.

5. The semiconductor device according to claim 1 , wherein the second oxide semiconductor film comprises zinc and has a composition where an atomic ratio of indium, gallium, and zinc is substantially 1:1:1.

6. The semiconductor device according to claim 1 , wherein the first oxide semiconductor film or the second oxide semiconductor film comprises a c-axis aligned crystalline oxide semiconductor.

7. The semiconductor device according to claim 1 , wherein the first oxide semiconductor film or the second oxide semiconductor film comprises an amorphous oxide semiconductor.

8. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer further comprises a third oxide semiconductor film,
wherein the first oxide semiconductor film is interposed between the second oxide semiconductor film and the third oxide semiconductor film, and
wherein the third oxide semiconductor film comprises indium and a Group 13 element other than the indium and has a composition where an atomic percent of the indium is less than or equal to an atomic percent of the Group 13 element other than the indium.

9. The semiconductor device according to claim 8 , wherein the third oxide semiconductor film comprises a c-axis aligned crystalline oxide semiconductor.

10. The semiconductor device according to claim 8 , wherein the third oxide semiconductor film comprises an amorphous oxide semiconductor.

11. The semiconductor device according to claim 8 ,
wherein the Group 13 element other than the indium is gallium, and
wherein the first oxide semiconductor film comprises zinc and has a composition where an atomic ratio of indium, gallium, and zinc is substantially 3:1:2.

12. The semiconductor device according to claim 8 ,
wherein the Group 13 element other than the indium is gallium, and
wherein the second oxide semiconductor film comprises zinc and has a composition where an atomic ratio of indium, gallium, and zinc is substantially 1:3:2.

13. The semiconductor device according to claim 8 ,
wherein the Group 13 element other than the indium is gallium, and
wherein the third oxide semiconductor film comprises zinc and has a composition where an atomic ratio of indium, gallium, and zinc is substantially 1:1:1.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Okazaki Kenichi
• Watanabe Masahiro
• Handa Takuya

Classifications

• H01L27/1225

  Electricity · mapped topic

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2300/0439

  Pixel structures · CPC title

• H01L27/124

  Electricity · mapped topic

• G09G3/3225

  using an active matrix · CPC title