Low temperature P+ polycrystalline silicon material for non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9793474-B2
Application number	US-201414188622-A
Country	US
Kind code	B2
Filing date	Feb 24, 2014
Priority date	Apr 20, 2012
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

First claim

What is claimed is:

1. A memory device, comprising:
a first electrode;
a second electrode having a portion comprising an active conductive material;
a resistive switching material configured in an intersection region between the first electrode and the second electrode; and
a buffer layer material that has a p+ impurity characteristic disposed in between the first electrode and the resistive switching material, wherein the buffer layer material comprises a polycrystalline p+ silicon germanium material and a polycrystalline p+ silicon material.

2. The device of claim 1 wherein the second electrode comprises a metal material selected from a group consisting of: silver, copper, tungsten, aluminum, or a combination.

3. The device of claim 1 wherein the resistive switching material comprises a silicon material having an intrinsic semiconductor characteristic.

4. The device of claim 3 wherein the silicon material having the intrinsic semiconductor characteristic comprises an amorphous silicon material or an amorphous silicon germanium material.

5. The device of claim 1 wherein the resistive switching material comprises a zinc oxide material.

6. The device of claim 1 wherein the buffer layer material is characterized by a work function and barrier height that results in an energy barrier between active conductive material particles in the resistive switching layer and the buffer layer material.

7. The device of claim 6 wherein the energy barrier facilitates an intrinsically controllable on-state current magnitude independent of current compliance circuitry, in response to application of a first voltage.

8. The device of claim 7 wherein the first voltage is a forward bias voltage comprising of a positive voltage applied to the second electrode with respect to the first electrode upon programming to cause a filament structure derived from the active conductor material to form in a portion of the resistive switching material.

9. The device of claim 8 wherein the filament structure is configured to retract upon application of a backward bias voltage comprising of a negative voltage applied to the second electrode with respect to the first electrode after programming.

10. The device of claim 1 , wherein the polycrystalline p+ silicon material has a thickness within a range of about 30 nanometers (nm) to about 50 nm.

11. The device of claim 1 , wherein the buffer layer material comprises a first silicon-bearing layer formed of the polycrystalline p+ silicon germanium material underlying a second silicon-bearing layer formed of the polycrystalline p+ silicon material.

12. The device of claim 11 , wherein the first silicon-bearing layer formed of polycrystalline p+ silicon germanium material has a dopant concentration between about 1E20 and about 3E20 particles per cm 3 .

13. The device of claim 11 , wherein the second silicon-bearing layer formed of polycrystalline p+ silicon material has a dopant concentration between about 2E20 and about 4E20 particles per cm 3 .

14. A memory device, comprising:
a substrate having a top surface;
an insulator layer overlying the top surface of the substrate;
a first wiring structure within or overlying the insulator layer and extending along a first direction;
a buffer layer comprising at least two silicon-bearing sub-layers, wherein the buffer layer has a p+ impurity characteristic and each of the at least two silicon-bearing sub-layers have a p+ impurity characteristic;
a resistive switching layer overlying the buffer layer; and
a second wiring structure overlying the resistive switching layer and extending along a second direction that is not parallel with the first direction.

15. The device of claim 14 , wherein the at least two silicon-bearing sub-layers comprise a polycrystalline p+ silicon material sub-layer and a polycrystalline p+ silicon germanium material sub-layer.

16. The device of claim 15 , wherein the polycrystalline p+ silicon material sub-layer is overlying the polycrystalline p+ silicon germanium material sub-layer.

17. The device of claim 15 , wherein the polycrystalline p+ silicon germanium material sub-layer has a composition of between about 0.2 and about 0.3 parts germanium.

18. The device of claim 14 , wherein the second wiring structure further comprises an active conductive material in electrical contact with the resistive switching material and with the second wiring structure.

19. The device of claim 18 , further comprising:
a dielectric material overlying the resistive switching material; and
a via structure formed in a portion of the dielectric material overlying the resistive switching material, wherein the active conductive material is situated at least in part within the via structure and facilitates ohmic contact between the resistive switching material and the second electrode.

20. The device of claim 18 , wherein the buffer layer is characterized by a work function and barrier height that results in an energy barrier between particles of the active conductive material in the resistive switching layer and the buffer layer material.

Assignees

• Crossbar Inc

Inventors

• Sun Xin
• Jo Sung Hyun
• Kumar Tanmay

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H01L21/0262

  Electricity · mapped topic