Controlling on-state current for two-terminal memory

Patent metadata

Field	Value
Publication number	US-9093635-B2
Application number	US-201313910402-A
Country	US
Kind code	B2
Filing date	Jun 5, 2013
Priority date	Mar 14, 2013
Publication date	Jul 28, 2015
Grant date	Jul 28, 2015

Abstract

Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate layer including a first electrode; and
a two-terminal memory layer comprising:
a first layer coupled to the first electrode, wherein the first layer comprises a first semiconductor material in an amorphous phase;
a second layer coupled to the first layer, wherein the second layer comprises a second semiconductor material in a polycrystalline phase;
a resistive switching material (RSLM) layer coupled to the second layer;
an active metal layer coupled to the resistive switching material layer; and

a second electrode coupled to the active metal layer.

2. The memory device of claim 1 , wherein the substrate layer comprises a complementary metal oxide semiconductor (CMOS).

3. The memory device of claim 1 , wherein the two-terminal memory layer comprises a resistive random access memory (RRAM) cell.

4. The memory device of claim 1 , wherein the second semiconductor material is a p-type conductive semiconductor material comprising polycrystalline silicon germanium (SiGe).

5. The memory device of claim 1 , wherein the first semiconductor material is a p-type resistive semiconductor material comprising amorphous SiGe.

6. The memory device of claim 1 , wherein a thickness of the second semiconductor material is within a range of about 5 nanometers to about 50 nanometers and a thickness of the first semiconductor material is within a range of about 20 nanometers to about 200 nanometers.

7. The memory device of claim 1 , wherein a resistivity of the second semiconductor material is within a range of about 0.001 ohm-centimeters to about 0.5 ohm-centimeters and a resistivity of the first semiconductor material is within a range of about 5 ohm-centimeters to about 50 ohm-centimeters.

8. The memory device of claim 1 , wherein the resistive switching material layer comprises a silicon sub-oxide.

9. The memory device of claim 1 , wherein:
the active metal layer is selected from a group consisting of: silver (Ag), gold (Au), titanium (Ti), nickel (Ni), and aluminum (Al).

10. A semiconductor device comprising:
a substrate comprising a first electrode;
a resistive material layer disposed upon the substrate and in contact with the first electrode, wherein the resistive material layer comprises a semiconductor material in an amorphous phase;
a conductive material layer disposed upon the resistive material layer, wherein the conductive material layer comprises the semiconductor material in a polycrystalline phase;
a resistive switching material layer disposed upon the conductive material layer, wherein the resistive switching material layer comprises a silicon sub-oxide;
an active metal layer disposed upon the resistive switching material layer; and
a second electrode in contact with the active material layer.

11. The semiconductor device of claim 10 wherein the semiconductor material comprises silicon germanium material.

12. The semiconductor device of claim 10 wherein the semiconductor material comprises p-type silicon germanium material.

13. The semiconductor device of claim 10
wherein a thickness of the conductive material layer is within a range of about 5 nanometers to about 50 nanometers; and
wherein a thickness of the resistive material is within a range of about 20 nanometers to about 200 nanometers.

14. The semiconductor device of claim 10
wherein the resistive switching material layer comprises a conductive filament formed therein; and
wherein the conductive filament comprises metal particles derived from the active metal layer.

15. The semiconductor device of claim 10
wherein the resistive material layer is characterized by a first thickness;
wherein the conductive material layer is characterized by a second thickness;
wherein a series resistance is associated with the resistive material layer and the conductive material layer; and
wherein the series resistance is associated with the first thickness and the second thickness.

16. The semiconductor device of claim 15 wherein the series resistance is proportional to the first thickness.

17. The semiconductor device of claim 10
wherein the resistive switching material layer comprises a titanium sub-oxide;
wherein the silicon sub-oxide is disposed upon the conductive material layer;
wherein the titanium sub-oxide is disposed upon the silicon sub-oxide; and
wherein the active metal layer is disposed upon the titanium sub-oxide.

18. The semiconductor device of claim 10 wherein the active metal layer is selected from a group consisting of: gold (Au), titanium (Ti), nickel (Ni), and aluminum (Al).

19. The semiconductor device of claim 10 wherein the substrate comprises a plurality of CMOS compatible devices selected from a group consisting of: logic, drivers, a processor.

Assignees

• Crossbar Inc

Inventors

• Kim Kuk-Hwan
• Lu Ping
• Chen Chen-Chun
• Jo Sung Hyun

Classifications

• H01L45/12

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/06 Primary

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic