Method of fabricating flash memory device

Patent metadata

Field	Value
Publication number	US-9793155-B2
Application number	US-201514734287-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Aug 20, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

First claim

What is claimed is:

1. A method of fabricating patterns for a flash memory device, the method comprising:
sequentially forming an etching object layer and a lower sacrificial layer on a substrate;
forming an upper sacrificial pattern structure including an upper sacrificial pad portion and an upper sacrificial line portion on the lower sacrificial layer;
forming an upper spacer covering a side wall of the upper sacrificial pattern structure;
forming a lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion by etching the lower sacrificial layer, using the upper sacrificial pad portion and the upper spacer as an etch mask;
forming a lower spacer layer covering the lower sacrificial pattern structure; and
forming a lower mask pattern including at least one line mask, at least one bridge mask, and at least one pad mask, by etching the lower spacer layer and at least a portion of the lower sacrificial pattern structure,
wherein an upper surface of the lower sacrificial line portion includes a step portion.

2. The method of claim 1 , wherein a line width of the at least one bridge mask is greater than a line width of the at least one line mask.

3. The method of claim 1 , wherein at least one of the line masks is formed of a remaining portion of the lower spacer layer, and at least one of the bridge masks is formed of a remaining portion of the lower spacer layer and a remaining portion of the lower sacrificial pattcrn structure.

4. The method of claim 1 , further comprising: forming a line pattern, a bridge pattern, and a contact pad by etching the etching object layer by using at least one of the line masks, at least one of the bridge masks, and at least one of the pad masks, respectively, as an etch mask.

5. The method of claim 4 , wherein the line pattern comprises a word line or a bit line.

6. The method of claim 4 , wherein an end of the line pattern is connected to at least one of the bridge pattern and the contact pad.

7. The method of claim 1 , wherein an upper surface of the lower sacrificial pad portion includes a step portion.

8. The method of claim 1 , wherein the forming of the upper spacer includes:
forming an upper spacer layer covering the upper sacrificial pattern structure;
forming a first photoresist pattern covering a portion of the upper spacer layer which is located at a side wall of the upper sacrificial line portion, and exposing a portion of the upper spacer layer which is located at the other side wall of the upper sacrificial line portion facing the side wall of the upper sacrificial line portion; and
forming the upper spacer by using the first photoresist pattern as an etch mask.

9. The method of claim 1 , wherein the forming of the upper spacer comprises:
forming an upper spacer layer on the upper sacrificial pattern structure; and
removing a portion of the upper spacer layer, and the upper sacrificial line portion.

10. A method of fabricating a flash memory device, the method comprising: sequentially forming an etching object layer and a lower sacrificial layer on a substrate;
forming a plurality of upper sacrificial pattern structures on the lower sacrificial layer;
forming a plurality of upper spacers by covering side walls of the upper sacrificial pattern structures; forming a plurality of lower sacrificial pattern structures, by etching the lower sacrificial layer using the upper spacers as an etch mask;
forming a lower spacer layer covering the plurality of lower sacrificial pattern structures;
forming a lower mask pattern, including a plurality of line masks, by etching the lower spacer layer and at least a portion of lower sacrificial pattern structure; and
forming a first line pattern, and a second line pattern by etching the etching object layer, by using the lower mask pattern as an etch mask,
wherein the first line pattern is a selection line including a string selection line (SSL) or a ground selection line (GSL), and each of the second line patterns is a word line (WL).

11. The method of fabricating a flash memory device of claim 10 , wherein the forming of the etching object layer includes sequentially forming a stack of tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a gate conductive layer on the substrate.

12. A method of fabricating a flash memory device, the method comprising:
sequentially forming an etching object layer and a lower sacrificial layer on a substrate;
forming a plurality of upper sacrificial pattern structures on the lower sacrificial layer;
forming a plurality of upper spacers by covering side walls of the upper sacrificial pattern structures; forming plurality of lower sacrificial pattern structures, by etching the lower sacrificial layer using the upper spacers as an etch mask;
forming a lower spacer layer covering the plurality of lower sacrificial pattern structures;
forming a lower mask pattern, including a plurality of line masks, by etching the lower spacer layer and at least a portion of lower sacrificial pattern structure; and
forming a first line pattern, and a second line pattern by etching the etching object layer, by using the lower mask pattern as an etch mask, wherein the forming of the upper spacer includes
forming an upper spacer layer covering the upper sacrificial pattern structures;
forming a first photoresist pattern exposing a portion of the upper spacer layer such that the photoresist covers a region of the upper spacer layer at a first side wall of the upper sacrificial pattern structure; and
forming the upper spacer by using the first photoresist pattern as an etch mask.

13. The method of fabricating a flash memory device of claim 12 , wherein
the first side wall of the upper sacrificial pattern structure is located in an area perpendicularly overlapping a string selection line (SLL) or a ground selection line (GSL), and
the etching object layer includes a blocking insulator layer having a butting contact below the first side wall.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seong Ho-Jun
• Han Jee-Hoon

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10W20/01 Primary

  Manufacture or treatment · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title