Segmented edge protection shield

US9793129B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9793129-B2
Application numberUS-201514717780-A
CountryUS
Kind codeB2
Filing dateMay 20, 2015
Priority dateMay 20, 2015
Publication dateOct 17, 2017
Grant dateOct 17, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

First claim

Opening claim text (preview).

What is claimed is: 1. A segmented edge protection shield for plasma dicing a wafer, comprising: an outer structure that defines an interior annular edge configured to correspond to the circumferential edge of the wafer, wherein the annular edge comprises a continuous ring-shaped surface; a plurality of plasma shield edge segments contacting the annular edge, wherein each one of the plurality of plasma shield edge segments is defined by an inner edge that is interior to and concentric to the annular edge and side edges that extend between the inner edge and the annular edge; and a plurality of gaps exposing portions of the annular edge between adjacent ones of the plurality of plasma shield edge segments. 2. The segmented edge protection shield of claim 1 , wherein the side edges of adjacent ones of the plurality of plasma shield edge segments are approximately parallel. 3. The segmented edge protection shield of claim 1 , wherein the side edges of the adjacent ones of the plurality of plasma shield edge segments intersect the annular edge. 4. The segmented edge protection shield of claim 1 , wherein a distance between the inner edge of the plurality of plasma shield edge segments and the annular edge is about 1 mm to about 10 mm. 5. The segmented edge protection shield of claim 1 , wherein a distance between the side edges of the adjacent ones of the plurality of plasma shield edge segments is about 1 mm to about 10 mm. 6. A wafer comprising: a plurality of singulated dies, wherein each die of the plurality of singulated dies is separated from each other by a gap; and a plurality of singulated wafer edge areas that are spaced apart around a circumferential edge of the wafer, wherein each of the plurality of singulated wafer edge areas is separated from each other by a gap, wherein each of the plurality of singulated wafer edge areas is larger than each of the plurality of singulated dies. 7. The wafer of claim 6 , wherein the plurality of singulated wafer edge areas comprise interconnected kerf lines of partial die that are adjacent to and exterior to a plurality of edge segments, wherein each one of the plurality of edge segments is defined by an inner edge that is concentric to the circumferential edge of the wafer and side edges that extend between the inner edge and the circumferential edge of the wafer. 8. The wafer of claim 7 , wherein the plurality of singulated wafer edge areas comprise the inner edge of the plurality of edge segments having a length that is greater than a maximum distance between adjacent kerf lines. 9. The wafer of claim 7 , wherein the plurality of singulated wafer edge areas comprise the side edges of the plurality of edge segments having a same length. 10. The wafer of claim 7 , wherein the singulated die comprise singulated die between the side edges of adjacent ones of the plurality of edge segments, wherein a distance between the side edges of the adjacent ones of the plurality of edge segments is greater than a maximum distance between adjacent kerf lines. 11. The wafer of claim 7 , wherein a distance between the inner edge of the plurality of edge segments and the circumferential edge of the wafer is about 1 mm to about 10 mm. 12. The wafer of claim 7 , wherein a distance between the side edges of the adjacent ones of the plurality of edge segments is about 1 mm to about 10 mm. 13. A segmented edge protection shield for plasma dicing a wafer, comprising: an outer structure that defines an interior annular edge configured to correspond to the circumferential edge of the wafer; and a plurality of plasma shield edge segments contacting the annular edge, wherein each one of the plurality of plasma shield edge segments is defined by an inner edge that is interior to and concentric to the annular edge and side edges that extend between the inner edge and the annular edge, wherein the outer structure comprises a plurality of structures joining adjacent ones of the plurality of plasma shield edge segments, wherein the total number of the plurality of structures is the same as the total number of the plurality of plasma shield edge segments.

Assignees

Inventors

Classifications

  • Apparatus for mechanical treatment or grinding or cutting · CPC title

  • H10P54/00Primary

    Cutting or separating of wafers, substrates or parts of devices · CPC title

  • H10P50/242Primary

    of Group IV materials · CPC title

  • Focus rings · CPC title

  • Shields, e.g. dark space shields, Faraday shields · CPC title

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Frequently asked questions

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What does patent US9793129B2 cover?
A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. T…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 17 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).