Method for base contact layout, such as for memory

Patent metadata

Field	Value
Publication number	US-9786719-B2
Application number	US-201213414329-A
Country	US
Kind code	B2
Filing date	Mar 7, 2012
Priority date	Mar 7, 2012
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Embodiments disclosed herein may relate to forming a base contact layout in a memory device.

First claim

The invention claimed is:

1. A method, comprising:
forming a base contact layout for a memory array, the layout comprising:
a plurality of word-line interconnect portions extending continuously in a first direction alongside one another, each word-line interconnect portion tapering from a first width to a second width less than the first width; and
a pattern of base interconnect areas for the plurality of word-line interconnect portions, wherein each word-line interconnect portion has a plurality of associated base interconnect areas, wherein at least one base interconnect area contacts a first pair of base contact pillars, wherein a second pair of base contact pillars different than the first pair of base contact pillars is positioned between base interconnect areas located along a second direction different from the first direction, the second pair of base contact pillars being separated from the plurality of word-line interconnect portions, each base interconnect area having a first dimension extending in the first direction that is at least three times larger than the second width of the word-line interconnect portions, the second width extending in the second direction; and
wherein each base interconnect area is longer along the first direction than along the second direction.

2. The method of claim 1 , further comprising forming one or more selector transistors corresponding to one or more memory cells of the memory array, wherein the one or more selector transistors individually comprise a base component corresponding to a respective base interconnect area.

3. The method of claim 2 , wherein the one or more selector transistors comprise one or more bipolar junction transistors.

4. The method of claim 3 , wherein the forming the one or more selector transistors comprises forming the base component at least in part by depositing an epitaxial semiconductor material over a collector material.

5. The method of claim 4 , wherein the depositing the epitaxial semiconductor material comprises depositing a silicon material over the collector material.

6. The method of claim 5 , wherein the depositing the silicon material over the collector material comprises depositing the silicon material over the collector material that is later to be n-doped.

7. The method of claim 4 , wherein the forming the one or more selector transistors further comprises forming one or more trenches in the epitaxial semiconductor material.

8. The method of claim 7 , wherein the forming the one or more trenches in the epitaxial semiconductor material comprises forming the one or more trenches in accordance with a shallow-trench isolation configuration.

9. The method of claim 1 , wherein forming the base contact layout comprises forming isolation trenches immediately adjacent and on opposing sides of the base interconnect areas, the isolation trenches elongated in a bit-line direction.

10. The method of claim 9 , wherein further comprising forming memory cells on the opposing sides of the base interconnect areas, the memory cells immediately adjacent the isolation trenches.

11. The method of claim 1 , wherein the first direction comprises:
a word-line direction.

12. The method of claim 1 , wherein the second direction comprises:
a bit-line direction.

13. The method of claim 1 , wherein at least some of the word-line interconnect portions taper downward.

14. The method of claim 1 , wherein at least one base interconnect area is in electronic communication with a memory cell of the memory array.

15. The method of claim 1 , wherein the second pair of base contact pillars is associated with a first word-line interconnect portion, and wherein one of the base interconnect areas located along the second direction is associated with a second word-line interconnect portion different from the first word-line interconnect portion.

16. The method of claim 1 , wherein the first pair of base contact pillars is electrically coupled to the plurality of word-line interconnect portions via the at least one base interconnect area.

Assignees

• Rigano Antonino
• Pellizzer Fabio
• Capetti Gianfranco
• Micron Technology Inc

Inventors

• Rigano Antonino
• Pellizzer Fabio
• Capetti Gianfranco

Classifications

• H01L27/101

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L27/2436 Primary

  Electricity · mapped topic