Method for manufacturing semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9786679-B2
Application number	US-201514844250-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Mar 16, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor memory device comprising:
forming a stacked body on a substrate, the stacked body including a plurality of first layers and a plurality of second layers respectively provided between the first layers;
forming a mask layer on the stacked body;
forming a stopper film of a different material from a material of the stacked body in a part of the mask layer;
forming a plurality of mask holes in the mask layer, the mask holes including a first mask hole overlapping on the stopper film;
by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film; and
forming memory films and channel bodies in the holes.

2. The method according to claim 1 , further comprising forming a slit that penetrates the stacked body and separates the stacked body into a plurality of pieces, wherein the stopper film is formed in the slit.

3. The method according to claim 2 , further comprising expanding a width of an upper portion of the slit.

4. The method according to claim 2 , wherein forming the stopper film includes forming a first film, and forming a second film of a different material from a material of the first film on the first film.

5. The method according to claim 4 , wherein the first film includes a silicon nitride film, and the second film includes a tungsten film or a carbon film.

6. The method according to claim 3 , wherein forming the stopper film includes forming a first film, and forming a second film of a different material from a material of the first film on the first film.

7. The method according to claim 6 , wherein the first film includes a silicon nitride film, and the second film includes a tungsten film or a carbon film.

8. The method according to claim 3 , wherein forming the stopper film includes forming a first film under the upper portion of the slit, and forming a second film of a different material from a material of the first film in the upper portion.

9. The method according to claim 8 , wherein the first film includes a silicon nitride film, and the second film includes a tungsten film or a carbon film.

10. The method according to claim 3 , wherein, suppose that two directions in parallel to a major surface of the substrate and orthogonal to each other are a first direction and a second direction,
the slit extends in the first direction, and
a width of the upper portion of the slit in the second direction is larger than a diameter of the mask hole.

11. The method according to claim 2 , wherein forming the stacked body includes forming electrode layers as the first layers, and insulating layers as the second layers.

12. The method according to claim 11 , further comprising:
removing the stopper film after forming the memory films and the channel bodies in the holes;
metal-siliciding end portions at the slit side in the electrode layers after removing the stopper film; and
forming an insulating film in the slit after forming the metal silicide.

13. The method according to claim 1 , further comprising forming a slit that separates the stacked body into a plurality of pieces after forming the memory films and the channel bodies.

14. The method according to claim 13 , wherein the stopper film is formed on a region in which the slit is to be formed.

15. The method according to claim 13 , further comprising:
removing the first layers by etching through the slit; and
forming electrode layers in spaces in which the first layers have been removed.

16. The method according to claim 15 , further comprising forming a source layer in the slit.

17. The method according to claim 14 , further comprising:
removing the first layers by etching through the slit; and
forming electrode layers in spaces in which the first layers have been removed.

18. The method according to claim 17 , further comprising forming a source layer within the slit.

19. The method according to claim 1 , wherein the plurality of mask holes are periodically arranged.

20. The method according to claim 19 , wherein the plurality of mask holes are arranged in translational transitional symmetry.

Assignees

• Toshiba Memory Corp

Inventors

• Fukuzumi Yoshiaki
• Aochi Hideaki
• Omura Mitsuhiro

Classifications

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title