Semiconductor device including multilayer wiring layer

Patent metadata

Field	Value
Publication number	US-9786668-B2
Application number	US-201615148000-A
Country	US
Kind code	B2
Filing date	May 6, 2016
Priority date	Jan 14, 2011
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a driver circuit;
a multilayer wiring layer over the driver circuit, the multilayer wiring layer comprising a wiring which comprises copper;
a memory cell over the multilayer wiring layer, wherein the memory cell overlaps with the driver circuit, the memory cell comprising a capacitor and a transistor which comprises a channel region, a source, a drain, and a gate,
wherein the capacitor is formed over the gate of the transistor and comprises a first layer comprising a first conductive material and a second layer comprising a second conductive material, the first layer being electrically connected to one of the source and the drain of the transistor,
wherein a cross-section of the capacitor shows a portion of the second layer comprised between first and second portions of the first layer, a first side edge of the portion of the second layer facing a side edge of the first portion of the first layer, a second side edge of the portion of the second layer facing a side edge of the second portion of the first layer, and
wherein the memory cell is operationally connected to the driver circuit through the wiring.

2. The semiconductor memory device according to claim 1 , wherein the channel region of the transistor comprises an oxide semiconductor material.

3. The semiconductor memory device according to claim 1 ,
wherein the first and second side edges of the portion of the second layer and the side edges of the first and second portions of the first layer are substantially vertical.

4. The semiconductor memory device according to claim 1 , wherein the capacitor and the channel region overlap with each other.

5. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is a DRAM memory device.

6. The semiconductor memory device according to claim 1 , wherein the driver circuit comprises a transistor comprising a channel region formed in a single crystal semiconductor substrate.

7. A driver circuit of a display device comprising the semiconductor memory device according to claim 1 as a video RAM.

8. A microprocessor comprising the semiconductor memory device according to claim 1 as a main memory.

9. A semiconductor memory device comprising:
a driver circuit comprising a first transistor comprising a channel region formed in a single crystal semiconductor substrate;
a multilayer wiring layer over the driver circuit, the multilayer wiring layer comprising a wiring which comprises copper; and
a memory cell over the multilayer wiring layer, wherein the memory cell overlaps with the driver circuit, the memory cell comprising a capacitor and a second transistor, the second transistor comprising a channel region, a source, a drain and a gate,
wherein the capacitor comprises a first electrode having a groove, a first insulating layer over the first electrode, and a second electrode over the first insulating layer, wherein part of the second electrode is formed in the groove,
wherein the groove overlaps with the channel region of the second transistor,
wherein the first electrode of the capacitor is electrically connected to one of the source and the drain of the second transistor, and
wherein the memory cell is operationally connected to the driver circuit through the wiring.

10. The semiconductor memory device according to claim 9 , wherein the channel region of the second transistor comprises an oxide semiconductor material.

11. The semiconductor memory device according to claim 9 , wherein the semiconductor memory device is a DRAM memory device.

12. A driver circuit of a display device comprising the semiconductor memory device according to claim 9 as a video RAM.

13. A microprocessor comprising the semiconductor memory device according to claim 9 as a main memory.

14. A microprocessor comprising:
a CPU;
a cache memory operationally connected to the CPU; and
a main memory operationally connected to the CPU, the main memory comprising:
a driver circuit comprising a first transistor comprising a channel region formed in a single crystal semiconductor substrate;
a multilayer wiring layer over the driver circuit, the multilayer wiring layer comprising a wiring which comprises copper; and
a memory cell over the multilayer wiring layer, wherein the memory cell overlaps with the driver circuit, the memory cell comprising a capacitor and a second transistor, the second transistor comprising a channel region, a source, a drain and a gate,

wherein the capacitor comprises a first electrode having a groove, a first insulating layer over the first electrode, and a second electrode over the first insulating layer, wherein part of the second electrode is formed in the groove,
wherein the groove overlaps with the channel region of the second transistor,
wherein the first electrode of the capacitor is electrically connected to one of the source and the drain of the second transistor, and
wherein the memory cell is operationally connected to the driver circuit through the wiring.

15. The microprocessor according to claim 14 , wherein the channel region of the second transistor comprises an oxide semiconductor material.

16. A semiconductor memory device comprising:
a driver circuit;
a multilayer wiring layer over the driver circuit, the multilayer wiring layer comprising a wiring which comprises copper;
a memory cell over the multilayer wiring layer, wherein the memory cell overlaps with the driver circuit, the memory cell comprising a capacitor and a transistor which comprises a channel region, a source, a drain, and a gate,
wherein the capacitor comprises a first electrode and a second electrode over the first electrode,
wherein the first electrode has a depressed portion and the second electrode has a projecting portion toward the first electrode,
wherein a top surface of the depressed portion and a bottom surface of the projecting portion face each other, and
wherein the memory cell is operationally connected to the driver circuit through the wiring.

17. The semiconductor memory device according to claim 16 , wherein the channel region of the transistor comprises an oxide semiconductor material.

18. The semiconductor memory device according to claim 16 , wherein the capacitor and the channel region overlap with each other.

19. The semiconductor memory device according to claim 16 , wherein the semiconductor memory device is a DRAM memory device.

20. The semiconductor memory device according to claim 16 , wherein the driver circuit comprises a transistor comprising a channel region formed in a single crystal semiconductor substrate.

21. A driver circuit of a display device comprising the semiconductor memory device according to claim 16 as a video RAM.

22. A microprocessor comprising the semiconductor memory device according to claim 16 as a main memory.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Takemura Yasuhiko

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C5/10

  for interconnecting capacitors · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/43

  Layouts of interconnections · CPC title