Semiconductor device including multilayer wiring layer

Patent metadata

Field	Value
Publication number	US-9337345-B2
Application number	US-201414336118-A
Country	US
Kind code	B2
Filing date	Jul 21, 2014
Priority date	Jan 14, 2011
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first circuit;
a multilayer wiring layer overlapping the first circuit, the multilayer wiring layer comprising a wiring; and
a second circuit overlapping the multilayer wiring layer and comprising unit cells,
wherein the second circuit is electrically connected to the first circuit through the wiring,
wherein each unit cell comprises a transistor,
wherein the wiring includes copper or a copper alloy, and
wherein channel regions of the transistors are included in oxide semiconductor layers.

2. A semiconductor device comprising:
a first circuit comprising a part of a single crystal semiconductor substrate;
a multilayer wiring layer overlapping the first circuit, the multilayer wiring layer comprising a wiring; and
a second circuit overlapping the multilayer wiring layer and comprising unit cells,
wherein the second circuit is electrically connected to the first circuit through the wiring,
wherein each unit cell comprises a transistor,
wherein the wiring includes copper or a copper alloy, and
wherein channel regions of the transistors are included in oxide semiconductor layers.

3. The semiconductor device according to claim 2 , wherein the single crystal semiconductor substrate is a single crystal silicon substrate.

4. A semiconductor device comprising:
a first circuit;
a multilayer wiring layer overlapping the first circuit, the multilayer wiring layer comprising a wiring; and
a second circuit overlapping the multilayer wiring layer and comprising unit cells,
wherein the second circuit is electrically connected to the first circuit through the wiring,
wherein each unit cell comprises a transistor and a capacitor, an electrode of the capacitor being electrically connected to one of a source and a drain of the transistor,
wherein the wiring includes copper or a copper alloy, and
wherein channel regions of the transistors are included in oxide semiconductor layers.

5. The semiconductor device according to claim 4 , wherein the first circuit comprises a part of a single crystal semiconductor substrate.

6. The semiconductor device according to claim 4 ,
wherein the first circuit comprises a part of a single crystal semiconductor substrate, and
wherein the single crystal semiconductor substrate is a single crystal silicon substrate.

7. The semiconductor device according to claim 4 , wherein the capacitor is a stack capacitor.

8. The semiconductor device according to claim 4 , wherein for each unit cell, the capacitor is electrically connected to the first circuit through the source and the drain of the transistor.

9. The semiconductor device according to claim 1 , wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.

10. The semiconductor device according to claim 2 , wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.

11. The semiconductor device according to claim 4 , wherein the wiring is embedded in an insulating layer included in the multilayer wiring layer.

12. The semiconductor device according to claim 1 , wherein the first circuit is a driver circuit configured to drive the second circuit.

13. The semiconductor device according to claim 2 , wherein the first circuit is a driver circuit configured to drive the second circuit.

14. The semiconductor device according to claim 4 , wherein the first circuit is a driver circuit configured to drive the second circuit.

15. The semiconductor device according to claim 1 , wherein each unit cell is a memory cell.

16. The semiconductor device according to claim 2 , wherein each unit cell is a memory cell.

17. The semiconductor device according to claim 4 , wherein each unit cell is a memory cell.

18. The semiconductor device according to claim 1 , the semiconductor device being comprised in a display device.

19. The semiconductor device according to claim 2 , the semiconductor device being comprised in a display device.

20. The semiconductor device according to claim 4 , the semiconductor device being comprised in a display device.

21. A semiconductor device comprising:
a first circuit;
a multilayer wiring layer overlapping the first circuit, the multilayer wiring layer comprising a wiring; and
a second circuit overlapping the multilayer wiring layer and comprising a unit cell, the unit cell comprising:
a transistor comprising an oxide semiconductor layer, a source, a drain, and a gate; and
a stack capacitor over the gate of the transistor, an electrode of the stack capacitor being electrically connected to one of the source and the drain of the transistor,

wherein the first circuit is configured to drive the second circuit,
wherein the second circuit is electrically connected to the first circuit through the wiring, and
wherein a channel region of the transistor is included in the oxide semiconductor layer.

22. The semiconductor device according to claim 21 , wherein the first circuit comprises a part of a single crystal semiconductor substrate.

23. The semiconductor device according to claim 21 , wherein the stack capacitor and the oxide semiconductor layer overlap with each other.

24. A semiconductor device comprising:
a first circuit comprising a part of a single crystal semiconductor substrate;
a multilayer wiring layer overlapping the first circuit, the multilayer wiring layer comprising a wiring; and
a second circuit overlapping the multilayer wiring layer and comprising a unit cell, the unit cell comprising:
a transistor comprising an oxide semiconductor layer, a source, a drain, and a gate; and
a stack capacitor over the gate of the transistor, an electrode of the stack capacitor being electrically connected to one of the source and the drain of the transistor,

wherein the first circuit is configured to drive the second circuit,
wherein the second circuit is electrically connected to the first circuit through the wiring,
wherein a channel region of the transistor is included in the oxide semiconductor layer, and
wherein the stack capacitor and the oxide semiconductor layer overlap with each other.

25. The semiconductor device according to claim 21 , wherein the stack capacitor and the channel region overlap with each other.

26. The semiconductor device according to claim 24 , wherein the stack capacitor and the channel region overlap with each other.

27. The semiconductor device according to claim 21 , wherein the stack capacitor and the gate overlap with each other.

28. The semiconductor device according to claim 24 , wherein the stack capacitor and the gate overlap with each other.

29. The semiconductor device according to claim 21 , wherein the stack capacitor, the gate, and the oxide semiconductor layer overlap with each other.

30. The semiconductor device according to claim 24 , wherein the stack capacitor, the gate, and the oxide semiconductor layer overlap with each other.

31. The semiconductor device according to claim 21 , wherein the stack capacitor is electrically connected to the first circuit via the source and the drain of the transistor.

32. The semiconductor device according to claim 24 , wherein the stack capacitor is electrically connected to the first circuit via the source and the drain of the transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Takemura Yasuhiko

Classifications

• G11C5/10

  for interconnecting capacitors · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/43

  Layouts of interconnections · CPC title