Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD

Patent metadata

Field	Value
Publication number	US-9780113-B2
Application number	US-201514963803-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Feb 10, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a stacked structure on a substrate, the stacked structure including a stepwise shape;
forming a first interlayer dielectric covering the stacked structure,
the first interlayer dielectric including at least one step portion having a sloped surface connecting a first top surface to a second top surface,
the first top surface and the sloped surface defining a first angle that is an obtuse angle, and
a level of the second top surface being higher than a level of the first top surface; and

forming a second interlayer dielectric covering the first interlayer dielectric.

2. The method as set forth in claim 1 , wherein
the forming the stacked structure includes forming a plurality of step layers on the substrate,
the forming the plurality of step layers includes forming at least a first step layer and a second step layer stacked sequentially,
the first step layer includes an end portion exposed by the second step layer,
the second step layer includes a side surface adjacent to the end portion of the first step layer,
a second angle is defined by a top surface of the end portion of the first step layer and the side surface of the second step layer, and
the second angle is smaller than the first angle.

3. The method as set forth in claim 2 , wherein the second angle is between 85 and 95 degrees.

4. The method as set forth in claim 2 , wherein the sloped surface horizontally corresponds to the side surface of the second step layer.

5. The method as set forth in claim 2 , further comprising:
forming a vertical channel structure penetrating the first step layer and the second step layer on a device region of the substrate, wherein
the substrate includes the device region and a connection region,
the forming the plurality of step layers includes forming the first step layer and the second step layer on the device region and the connection region, and
the forming the stacked structure includes forming the stacked structure so the stepwise shape is on the connection region.

6. The method as set forth in claim 5 , further comprising:
forming a first contact; and
forming a second contact, wherein
the forming the plurality of step layers includes forming the first step layer by sequentially stacking a first electrode and a first electrode insulating layer,
the forming the plurality of step layers includes forming the second step layer by sequentially stacking a second electrode and a second electrode insulating layer,
the forming the first contact includes electrically connecting the first contact to the first electrode by forming the first contact to penetrate the first interlayer dielectric, the second interlayer dielectric, and the first electrode insulating layer on the connection region, and
the forming the second contact includes electrically connecting the second contact to the second electrode by forming the second contact to penetrate the first inter layer dielectric, the second interlayer dielectric, and the second electrode insulating layer on the connection region.

7. The method as set forth in claim 1 , wherein the first top surface and the second top surface are sloped with respect to a top surface of the substrate.

8. The method as set forth in claim 1 , wherein
the first angle is between 100 and 150 degrees.

9. A method for fabricating a semiconductor device, comprising:
forming a stacked structure on a substrate, the stacked structure including a stepwise shape and including a plurality of step layers;
forming a first interlayer dielectric covering the stacked structure using a deposition process with a side step coverage of greater than 0 percent and less than or equal to 50 percent; and
forming a second interlayer dielectric covering the first interlayer dielectric.

10. The method as set forth in claim 9 , wherein
the forming the first interlayer dielectric includes performing a high-density plasma chemical vapor deposition process using silane (SiH 4 ) gas.

11. The method as set forth in claim 9 , wherein the forming the second interlayer dielectric includes performing a deposition process with a higher side step coverage than that of the deposition process used to form the first interlayer dielectric.

12. The method as set forth in claim 11 , wherein
the forming the second interlayer dielectric includes performing a plasma enhanced chemical vapor deposition process using tetraethoxysilane (TEOS) gas.

13. The method as set forth in claim 9 , wherein
the first interlayer dielectric includes at least one step portion having a sloped surface connecting a first top surface to a second top surface,
a level of the second top surface is higher than a level of the first top surface, and
the first top surface and the sloped surface define a first angle that is between 100 and 150 degrees.

14. The method as set forth in claim 13 , wherein
the substrate includes a device region and a connection region,
the forming the stacked structure includes,
sequentially forming a first step layer and a second step layer on the substrate,
forming the stepwise shape by removing a portion of the second step layer on the connection region and exposing a portion of a top surface of the first step layer, and
forming vertical channel structures penetrating the plurality of step layers on the device region, and

the exposed top surface of the first step layer and a side surface of the second step layer define a second angle that is between 85 and 95 degrees.

15. The method as set forth in claim 14 , further comprising:
forming a first and a second contact hole;
forming a first and a second contact, wherein
the forming first step layer includes forming a first electrode and a first electrode insulating layer stacked sequentially,
the forming the second step layer includes forming a second electrode and a second electrode insulating layer stacked sequentially,
forming the first contact hole and the second contact hole includes,
forming the first contact hole through the first interlayer dielectric, the second interlayer dielectric, and the first electrode insulating layer to expose a top surface of the first electrode on the connection region, and
forming the second contact hole through the first interlayer dielectric, the second interlayer dielectric, and the second electrode insulating layer to expose a top surface of the second electrode on the connection region, and

the forming the first contact and the second contact includes filling the first contact hole and the second contact hole with the first contact and the second contact, respectively.

16. A method for fabricating a semiconductor device, comprising:
forming a stacked structure on a substrate,
the stacked structure including a plurality of step layers stacked on top of each other,
an end of the stacked structure having a stepwise shape defined by the step layers extending farther parallel to the substrate as the step layers become closer to the substrate; and

forming a plurality of interlayer dielectrics on the stacked structure,
the forming the plurality of interlayer dielectrics including forming a first interlayer dielectric covering at least the end of the stacked structure and having a first side step coverage over the end of the stacked structure,
the forming the plurality of interlayer dielectrics including forming a second interlayer dielectric covering at least the first interlayer dielectric and the end of the stacked structure,
the second interlayer dielectric having a second side

Assignees

• Im Jiwoon
• PARK Kwangchul
• Seo Jiyoun
• Lee Jongmyeong
• Jang Kyung-Tae
• CHUN Byungho
• Jung Won-Seok
• Choi Jongwan
• Han Tae-Jong
• Samsung Electronics Co Ltd

Inventors

• Im Jiwoon
• PARK Kwangchul
• Seo Jiyoun
• Lee Jongmyeong
• Jang Kyung-Tae
• CHUN Byungho
• Jung Won-Seok
• Choi Jongwan
• Han Tae-Jong

Classifications

• H10W20/098 Primary

  by filling between adjacent conductive parts · CPC title

• H01L27/11575

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L21/76837

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic