Flash cell structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9780101-B1
Application number	US-201615361065-A
Country	US
Kind code	B1
Filing date	Nov 24, 2016
Priority date	Nov 24, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

First claim

What is claimed is:

1. A flash cell structure, comprising:
a semiconductor substrate;
a stacked gate structure disposed on the semiconductor substrate, and the stacked gate structure comprising:
a floating gate insulated from the semiconductor substrate; and
a control gate disposed on the floating gate and insulated from the floating gate;

a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure;
a first dielectric layer disposed on a sidewall of the floating gate;
a second dielectric layer disposed on the first doped region;
a third dielectric layer covering the stacked gate structure, the first dielectric layer and the second dielectric layer; and
an erase gate disposed on the first dielectric layer and the second dielectric layer, wherein a thickness of the first dielectric layer between the erase gate and the floating gate is less than a thickness of the second dielectric layer between the erase gate and the first doped region, and a ratio of a total thickness of the second dielectric layer and the third dielectric layer between the erase gate and the first doped region to a total thickness of the first dielectric layer and the third dielectric layer between the erase gate and the floating gate is substantially from 1.05 to 1.16.

2. The flash cell structure according to claim 1 , wherein the first dielectric layer and the second dielectric layer are in contact with each other and are formed of a continuous dielectric layer.

3. The flash cell structure according to claim 1 , wherein a doping concentration of the first doped region at a depth of less than 100 nm is greater than 7 20 atoms/μm 3 .

4. The flash cell structure according to claim 1 , wherein the first doped region is formed by implanting first dopants at a first doping concentration of 5 14 atoms/μm 3 and a first energy of 60 keV and implanting second dopants at a second doping concentration of 1.8 15 atoms/μm 3 and a second energy of 20 keV, and the first dopants are the same as the second dopants.

5. The flash cell structure according to claim 1 , wherein a width of the floating gate is greater than a width of the control gate.

6. The flash cell structure according to claim 5 , wherein the stacked gate structure comprises a spacer disposed between the erase gate and the control gate.

7. The flash cell structure according to claim 1 , further comprising a fourth dielectric layer disposed on the control gate, and a thickness of the fourth dielectric layer being larger than the thickness of the first dielectric layer.

8. The flash cell structure according to claim 1 , further comprising a second doped region disposed in the semiconductor substrate and spaced apart from the first doped region, wherein the stacked gate structure is disposed between the first doped region and the second doped region.

9. A method of fabricating a flash cell structure, comprising:
forming a stacked gate structure on a semiconductor substrate, wherein the stacked gate structure comprises:
a floating gate insulated from the semiconductor substrate; and
a control gate disposed on the floating gate and insulated from the floating gate;

forming a first doped region in the semiconductor substrate at a side of the stacked gate structure and forming a first dielectric layer on a sidewall of the floating gate and a second dielectric layer on the first doped region, wherein a thickness of the first dielectric layer is less than a thickness of the second dielectric layer;
forming a third dielectric layer to cover the stacked gate structure, the first dielectric layer and the second dielectric layer; and
forming an erase gate on the third dielectric layer at the side of the stacked gate structure.

10. The method of fabricating the flash cell structure according to claim 9 , wherein forming the first doped region comprises performing a first implantation process and a second implantation process.

11. The method of fabricating the flash cell structure according to claim 10 , wherein a first doping concentration and a first energy of the first implantation process are respectively 5 14 atoms/μm 3 and 60 keV, and a second doping concentration and a second energy of the second implantation process are respectively 1.8 15 atoms/μm 3 and 20 keV.

12. The method of fabricating the flash cell structure according to claim 11 , wherein the second implantation process is performed after the first implantation process.

13. The method of fabricating the flash cell structure according to claim 11 , wherein first dopants of the first implantation process and second dopants of the second implantation process comprise arsenic.

14. The method of fabricating the flash cell structure according to claim 10 , wherein forming the first doped region further comprises performing a drive-in process after the first implantation process and the second implantation process.

15. The method of fabricating the flash cell structure according to claim 9 , wherein the first dielectric layer and the second dielectric layer are formed by performing a pretreatment process introducing nitrogen oxide.

16. The method of fabricating the flash cell structure according to claim 9 , wherein forming the first dielectric layer and the second dielectric layer further comprises forming a fourth dielectric layer on the control gate, and a thickness of the fourth dielectric layer being larger than the thickness of the first dielectric layer.

17. The method of fabricating the flash cell structure according to claim 9 , wherein forming the erase gate further comprises forming a word line on the semiconductor substrate at another side of the stacked gate structure.

18. The method of fabricating the flash cell structure according to claim 17 , further comprising forming a second doped region in the semiconductor substrate, wherein the second doped region is spaced apart from the first doped region, and the word line and the stacked gate structure are disposed between the first doped region and the second doped region.

Assignees

• United Microelectronics Corp

Inventors

• Zhang Sheng
• Ding Wenbo
• Han Xiaofei
• Pang Chien-Kee
• Chen Yu-Yang
• Zhang Jubao

Classifications

• H01L27/11521 Primary

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/788

  Electricity · mapped topic

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title