Packaged device with additive substrate surface modification

Patent metadata

Field	Value
Publication number	US-9780017-B2
Application number	US-201615346822-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Sep 26, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

First claim

The invention claimed is:

1. A method of surface modification, comprising:
providing at least one package substrate comprising a plurality of contact regions;
depositing an ink comprising a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step onto at least one of the plurality of contact regions;
sintering or curing said ink to form an ink residue; and
electrically connecting a semiconductor device to the ink residue after the step of sintering.

2. The method of claim 1 , wherein said depositing comprises inkjet printing using piezoelectric, thermal, acoustic, or electrostatic inkjet printing, screen printing, or flexographic printing.

3. The method of claim 1 , wherein said plurality of contact regions comprises a die pad and a plurality of contact pads of a lead frame.

4. The method of claim 1 , wherein said step of electrically connecting comprises connecting a bond pad of the semiconductor device to a respective contact region.

5. The method of claim 1 , wherein said step of electrically connecting comprises connecting the semiconductor device to a die pad.

6. The method of claim 5 , comprising depositing low surface energy material having a surface energy of less than 20 mN/m around at least one of said plurality of contact regions.

7. The method of claim 1 , wherein said material has a porosity of greater than 10% and comprises nanoparticles of a metal material.

8. The method of claim 7 , wherein said metal material is different than said plurality of contact regions.

9. The method of claim 1 , further comprising electroplating over said ink residue with a precious metal layer or a precious metal alloy layer.

10. The method of claim 1 , further comprising forming metal terminals on bond pads of the semiconductor device and connecting the metal terminals to the ink residue at respective ones of the plurality of contact regions.

11. A packaged semiconductor device, comprising:
a package substrate comprising a plurality of contact regions;
an integrated circuit (IC) having a plurality of bond pads;
a plurality of leads coupled between respective ones of said plurality of bond pads and respective ones of said plurality of contact regions; and
an ink residue of spaced apart metal islands on one of the contact regions providing a connection to said IC.

12. The packaged semiconductor device of claim 11 , wherein said plurality of leads comprise bond wires.

13. The packaged semiconductor device of claim 11 , wherein said bond pads are coupled to said contact regions by metal terminals in a flip chip arrangement so that said packaged semiconductor device comprises a flip chip package.

14. The packaged semiconductor device of claim 11 , wherein said ink residue is arranged in a pattern of islands to form a rough surface topology on at least one of said contact regions.

15. The packaged semiconductor device of claim 11 , wherein said plurality of leads comprise one of a ball grid array and a pin grid array.

16. The packaged semiconductor device of claim 11 , further comprising a precious metal layer or a precious metal alloy layer over said spaced apart metal islands.

17. A method of surface modification, comprising:
providing at least one package substrate comprising a plurality of contact regions;
depositing an ink onto one of the plurality of contact regions, the ink comprising a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step;
sintering or curing the ink to form a dielectric ink residue pattern;
forming a metal layer within the dielectric ink residue pattern; and
removing the dielectric ink residue pattern, thereby forming a plurality of spaced apart metal islands from the metal layer.

18. The method of claim 17 , wherein said depositing an ink comprises inkjet printing using piezoelectric, thermal, acoustic, or electrostatic inkjet printing, screen printing, or flexographic printing.

19. The method of claim 17 , comprising electrically connecting a semiconductor device to the metal islands.

20. The method of claim 17 , wherein said step of forming comprises one of electroless plating and electroplating.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Herbsommer Juan Alejandro
• Lin Yong
• Zhang Rongwei
• Castro Abram
• Romig Matthew David

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title