Compensating for lithographic limitations in fabricating semiconductor interconnect structures

US9779943B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9779943-B2
Application numberUS-201615053818-A
CountryUS
Kind codeB2
Filing dateFeb 25, 2016
Priority dateFeb 25, 2016
Publication dateOct 3, 2017
Grant dateOct 3, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method, comprising: forming a metal line pattern for an interconnect structure at a pitch below lithographic resolution; and forming at least one bridge between portions of adjacent metal lines, the at least one bridge being metal and situated perpendicular to the adjacent metal lines. 2. The method of claim 1 , wherein the metal line pattern and at least one bridge are formed from a tri-layer hard mask stack. 3. The method of claim 2 , wherein the tri-layer hard mask stack comprises a layer of silicon nitride between two layers of titanium nitride. 4. The method of claim 2 , further comprising: forming mandrels from a mandrel layer situated above the tri-layer hard mask stack; and forming spacers adjacent the mandrels. 5. The method of claim 4 , wherein forming the mandrels comprises using lithography and etching to remove portions of a mandrel layer over the tri-layer hard mask stack. 6. The method of claim 4 , wherein forming the spacers comprises: forming a conformal blanket dielectric layer over the mandrels; and removing portions of the conformal blanket dielectric layer. 7. The method of claim 6 , wherein forming the conformal blanket dielectric layer comprises using an atomic layer deposition process. 8. The method of claim 4 , further comprising removing portions of a top hard mask layer of the tri-layer hard mask stack situated in at least one opening between the spacers. 9. The method of claim 8 , further comprising removing exposed portions of a middle hard mask layer of the tri-layer hard mask stack while preserving at least one portion perpendicular to a direction of the at least one opening. 10. The method of claim 9 , wherein the removing while preserving comprises using lithography. 11. The method of claim 9 , further comprising forming a filler material layer in the at least one opening and up to a top surface of the mandrels. 12. The method of claim 11 , further comprising: removing the mandrels; and removing portions of the top hard mask layer exposed by removing the mandrels. 13. The method of claim 12 , further comprising removing exposed portions of the middle hard mask layer of the tri-layer hard mask stack while preserving at least one portion thereof in an X-direction. 14. The method of claim 13 , wherein the removing while preserving comprises using lithography. 15. The method of claim 13 , further comprising: removing the spacers and filler material layer; removing remaining portions of the top hard mask layer of the tri-layer hard mask stack; and removing exposed portions of a bottom hard mask layer of the tri-layer hard mask stack.

Assignees

Inventors

Classifications

  • using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

  • characterised by the processes involved to create the masks · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9779943B2 cover?
A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10P76/4085. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).