Method to controllably etch silicon recess for ultra shallow junctions

Patent metadata

Field	Value
Publication number	US-9773907-B2
Application number	US-201615070560-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	May 19, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
forming a sacrificial gate structure on a channel portion of a fin structure that is comprised of a silicon including material;
forming a gate sidewall spacer on sidewalls of the sacrificial gate structure;
forming a germanium including material on source and drain region portions of a fin structure;
driving germanium from the germanium including material into the source and drain region portions of the fin structure to provide an alloyed silicon and germanium portion of the fin structure adjacent to an interior portion of the fin structure comprised of silicon, wherein the driving of the germanium from the germanium including material into the fin structure includes a portion of germanium that diffused to a portion of the fin structure underlying the gate sidewall spacer;
removing the alloyed silicon and germanium portion selectively to the interior portion of the fin structure comprised of silicon;
and
replacing the sacrificial gate structure with a function gate structure.

2. The method of claim 1 , wherein the fin structures comprises 100 at. % silicon.

3. The method of claim 1 , wherein the germanium including material is silicon germanium comprising greater than 50 at. % germanium.

4. The method of claim 1 , wherein forming of an epitaxial source regions and epitaxial drain regions on the source and drain region portions of the fin structures includes a portion of epitaxial material that fills the trench underlying the gate sidewall spacer.

5. The method of claim 1 , wherein the alloyed portion is underlying a gate sidewall spacer by a dimension ranging from 1 nm to 6 nm.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H01L29/66

  Electricity · mapped topic

• H01L29/7848 Primary

  Electricity · mapped topic

• H01L29/66636

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic