Method to controllably etch silicon recess for ultra shallow junctions

Patent metadata

Field	Value
Publication number	US-9324867-B2
Application number	US-201414281364-A
Country	US
Kind code	B2
Filing date	May 19, 2014
Priority date	May 19, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
forming a sacrificial gate structure on a channel portion of a fin structure that is comprised of a silicon including material;
forming a gate sidewall spacer on sidewalls of the sacrificial gate structure;
forming a germanium including material on source and drain region portions of a fin structure;
driving germanium from the germanium including material into the source and drain region portions of the fin structure to provide an alloyed silicon and germanium portion of the fin structure adjacent to an interior portion of the fin structure comprised of silicon, wherein the driving of the germanium from the germanium including material into the fin structure includes a portion of germanium that diffused to a portion of the fin structure underlying the gate sidewall spacer;
removing the alloyed silicon and germanium portion selectively to the interior portion of the fin structure comprised of silicon;
forming epitaxial source regions and epitaxial drain regions on the source and drain region portions of the fin structure; and
replacing the sacrificial gate structure with a function gate structure.

2. The method of claim 1 , wherein the germanium including material is silicon germanium comprising greater than 50 at. % germanium.

3. The method of claim 1 , wherein the forming of the epitaxial source regions and epitaxial drain regions on the source and drain region portions of the fin structures comprises a material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon, compound semiconductors, and combinations thereof.

4. A method of forming a semiconductor device comprising:
forming a sacrificial gate structure on a channel portion of a fin structure that is comprised of a silicon including material;
forming a gate sidewall spacer on sidewalls of the sacrificial gate structure;
forming a germanium including material on source and drain region portions of a fin structure;
driving germanium from the germanium including material into the source and drain region portions of the fin structure to provide an alloyed silicon and germanium portion of the fin structure adjacent to an interior portion of the fin structure comprised of silicon, wherein the driving of the germanium from the germanium including material into the fin structure includes a portion of germanium that diffused to a portion of the fin structure underlying the gate sidewall spacer;
removing the alloyed silicon and germanium portion selectively to the interior portion of the fin structure comprised of silicon, wherein the removing the alloyed silicon and germanium portion selectively to the interior portion of the fin structure comprised of silicon also removes a portion of the fin structure including the germanium that diffused to under the gate sidewall spacer to provide a trench underling the gate sidewall spacer;
forming epitaxial source regions and epitaxial drain regions on the source and drain region portions of the fin structure; and
replacing the sacrificial gate structure with a function gate structure.

5. The method of claim 4 , wherein the forming of the epitaxial source regions and epitaxial drain regions on the source and drain region portions of the fin structures includes a portion of epitaxial material that fills the trench underlying the gate sidewall spacer.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title