Memory device having self-aligned cell structure

Patent metadata

Field	Value
Publication number	US-9773839-B2
Application number	US-201514790535-A
Country	US
Kind code	B2
Filing date	Jul 2, 2015
Priority date	Feb 6, 2009
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

First claim

What is claimed is:

1. A method comprising:
forming device structures over a substrate, the device structures insulated from each other by a first insulation material, each of the device structures including a width and a length, the length extending in a first direction;
removing a portion of the device structures to form trenches extending in a second direction perpendicular to the first direction;
forming a second insulation material in the trenches;
removing a first material from the device structures to expose a second material of the device structures; and
forming diodes over the second material, wherein forming the device structures includes:
forming the second material over the substrate and forming the first material over the second material;
forming a first masking structure over the first material and the second material, the first masking structure including first openings, each of the first openings having a width and a length, the length extending in the first direction; and
removing a portion of the first material at the first openings and a portion of the second material at the first openings such that an unremoved portion of the first material and an unremoved portion of the second material form at least a part of the device structures.

2. The method of claim 1 , wherein removing the portion of the device structures to form the trenches includes:
forming a second masking structure over the device structures, the second masking structure including second openings, each of the second openings having a width and a length, the length extending in the second direction; and
removing the first material at the second openings to form the trenches.

3. The method of claim 1 , wherein forming diodes includes: forming an epitaxial silicon over the second material to form a first portion of each of the diodes; and inserting impurities into the epitaxial silicon to form a second portion of each of the diode.

4. The method of claim 1 , wherein the first material includes insulation material and the second material includes semiconductor material.

5. A method comprising:
forming device structures over a substrate, the device structures insulated from each other by a first insulation material, each of the device structures including a width and a length, the length extending in a first direction;
removing a portion of the device structures to form trenches extending in a second direction perpendicular to the first direction;
forming a second insulation material in the trenches;
removing a first material from the device structures to expose a second material of the device structures; and
forming diodes over the second material, wherein forming the device structures includes:
forming the second material over the substrate, forming a third material over the second material, and forming the first material over the third material;
forming a first masking structure over the first material, the first masking structure including first openings, each of the first openings having a width and a length, the length extending in the first direction; and
removing a portion of the first material at the first openings, a portion of the second material at the first openings, and a portion of the third material at the first openings such that an unremoved portion of the first material and an unremoved portion of the second material, and an unremoved portion of the third material form at least a part of the device structures.

6. The method of claim 5 , wherein removing the portion of the device structures to form the trenches includes:
forming a second masking structure over the device structures, the second masking structure including second openings, each of the second openings having a width and a length, the length extending in the second direction; and
removing the first material at the second openings to form the trenches and leaving at least a portion of the third material in the trenches.

7. The method of claim 6 , wherein the first material includes insulation material, the second material includes semiconductor material, and the third material includes conductive material.

8. The method of claim 7 , wherein the third material includes a combination of nickel and silicon.

9. The method of claim 1 further comprising: forming memory elements over the diodes.

10. The method of claim 9 , wherein forming memory elements includes depositing chalcogenide material over the diodes.

11. A method comprising:
forming device structures over a substrate, the device structures insulated from each other by an insulation material, each of the device structures including a width and a length, the length extending in a first direction;
forming a masking structure over the device structures, the masking structure including openings such that a first portion of a first material of the device structures are exposed at the openings and a second portion of the first material is underneath the masking structure, each of the openings having a width and a length, the length extending in a second direction perpendicular to the first direction;
removing a first portion of a first material at the openings from the device structures to expose a first portion of a second material of the device structures; and
forming diodes over the first portion of the second material, wherein forming the device structures includes:
forming the second material over the substrate and forming the first material over the second material;
forming an additional masking structure over the first material and the second material, the additional masking structure including first openings, each of the first openings having a width and a length, the length extending in the first direction; and
removing a second portion of the first material at the first openings and a portion of the second material at the first openings such that an unremoved portion of the first material and an unremoved portion of the second material form at least a part of the device structures.

12. A method comprising:
forming device structures over a substrate, the device structures insulated from each other by an insulation material, each of the device structures including a width and a length, the length extending in a first direction;
forming a masking structure over the device structures, the masking structure including openings such that a first portion of a first material of the device structures are exposed at the openings and a second portion of the first material is underneath the masking structure, each of the openings having a width and a length, the length extending in a second direction perpendicular to the first direction;
removing a first portion of a first material at the openings from the device structures to expose a first portion of a second material of the device structures; and
forming diodes over the first portion of the second material, wherein forming the device structures includes:
forming the second material over the substrate, forming the first material over the second material, and forming a third material over the second material;
forming an additional masking structure over the first material, the second material, and the third material, the additional masking structure including first openings, each of the first openings having a width and a length, the length extending in the second first direction; and
removing a second portion of the first material at the first openings, a portion of the second material at the first openings, and a portion of the third material at the first openings such that an unremoved portion of the first material, an unremoved portion of the second material, and an unremoved port

Assignees

• Micron Technology Inc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• G11C2213/33

  Material including silicon · CPC title

• H01L45/1233

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic