Mark structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9773739-B2
Application number	US-201715397788-A
Country	US
Kind code	B2
Filing date	Jan 4, 2017
Priority date	Feb 3, 2016
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.

First claim

What is claimed is:

1. A method for forming a mark structure, comprising:
providing a substrate having a device region and a mark region including a first mark region and a second mark region surrounded by the first mark region;
sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate;
forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, a bottom of the first opening, a bottom of the first mark and a bottom of the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer;
forming a second opening exposing the device layer in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening; and
forming a conductive structure in the first opening and the second opening.

2. The method according to claim 1 , wherein:
the first mark includes a plurality of first mark trenches.

3. The method according to claim 2 , wherein forming the first mark, the first opening, and the first mark opening comprises:
forming a first pattern layer exposing portions of a surface of the mask layer corresponding to the first trench marks, the first opening, and the mark opening on the surface of the mask layer;
etching the mask aver and portions of the dielectric layer by a first etching process using the first pattern layer as an etching mask; and
removing the first pattern layer.

4. The method according to claim 2 , wherein:
the first mark includes a plurality of first mark protruding parts.

5. The method according to claim 4 wherein forming the mark, the first opening, and the first mark opening comprises:
forming a first pattern layer exposing an entire portion of a surface of the mask layer in the second mark region and portions of the surface of the mask layer in the device region and the first mark region, and covering a portion of the surface of the mask layer corresponding to the first mask protruding parts on the surface of the mask layer;
etching the mask layer and portions of the dielectric layer by a first etching process using the first pattern layer as an etching mask; and
removing the first pattern layer.

6. The method according to claim 1 , wherein:
the second mark includes a plurality of second mark trenches.

7. The method according to claim 6 , wherein forming the second mark and the second opening further comprises:
forming a second pattern layer exposing portions of a surface of the dielectric layer corresponding to the second mark trenches and the second opening on the mask layer;
etching the dielectric layer by a second etching process using the second pattern layer as an etching mask; and
removing the second pattern layer.

8. The method according to claim 7 , wherein:
an etching rate of the first etching process to the mask layer is greater than an etching rate of the second etching process to the mask layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• LU Dao Liang
• Zhang Hong Wei
• Feng Kui

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title