Method for manufacturing semiconductor device and alignment mark of semiconductor device

Patent metadata

Field	Value
Publication number	US-9401332-B2
Application number	US-201414197548-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Nov 22, 2013
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell region and a mark region, forming a first mask layer above the stacked layer, and forming a second mask layer above the first mask layer; forming the second mask layer into first mask pattern features and forming a first alignment mark pattern feature; forming second mask pattern features and then removing the first mask pattern features; opening part of the second mask pattern features and forming a third mask layer having an opening; removing part of the second mask pattern features; removing the third mask layer; forming a fourth mask layer; etching the first mask layer; removing the fourth mask layer and then removing the second mask pattern features; and etching the stacked layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device comprising:
forming an insulating film above a stacked body including a first layer as an uppermost layer;
forming a mark having a first opening above the stacked body via the insulating film;
etching the insulating film exposed from the first opening and the stacked body located under the first opening so as to form a second opening in the insulating film and the stacked body, the mark being transferred to the second opening; and
forming a second layer including a same material as the first layer in the second opening, wherein the process of the forming the second layer includes:
forming the second layer in the second opening and forming the second layer on the insulating film; and
removing the second layer formed on the insulating film and the insulating film so as to expose the first layer from the insulating film and making flush an upper surface of the second layer formed in the second opening and an upper surface of the first layer.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein
after removing the second layer, a third layer and the first layer is exposed, and
the third layer is made of a material different from that which the first layer is formed.

3. A method for manufacturing a semiconductor device comprising:
forming an insulating layer covering a first stacked body disposed in a memory cell region and a second stacked body disposed in a mark region, a height of a portion of the insulating layer above the second stacked body being lower than a height of a portion of the insulating layer above the first stacked body;
forming a mark having a first opening above the second stacked body via the insulating layer;
etching the insulating layer exposed from the first opening and the second stacked body located under the first opening in the mark region so as to form a second opening in the insulating layer and the second stacked body in the mark region, the mark being transferred to the second opening;
forming a second layer in the second opening in the mark region and forming the second layer on the insulating layer in the memory cell region and the mark region; and
removing the second layer formed on the insulating layer and the insulating layer in the memory cell region and leaving the second layer above the insulating layer with a lower height than the height of the portion of the insulating layer above the first stacked body so as to cover the second layer formed in the second opening with the second layer in the mark region.

4. An alignment mark of a semiconductor device comprising third portions having a first portion and a second portion surrounding the first portion and made of a material different from the first portion when viewed from above, an upper surface of the second portion being lower than an upper surface of the first portion,
wherein the third portions are arranged so as to oppose each other across a fourth portion when viewed from above and a height of the upper surface of the first portion is equal to a height of the upper surface of the fourth portion.

5. An alignment mark of a semiconductor device comprising third portions having a first portion and a second portion surrounding the first portion and made of a material different from the first portion when viewed from above, an upper surface of the second portion being lower than an upper surface of the first portion,
wherein the third portions are arranged so as to oppose each other across a fourth portion when viewed from above and the first portion and the fourth portion are made of a same material.

Assignees

• Toshiba Kk

Inventors

• Noda Kotaro

Classifications

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H01L2223/54426

  Electricity · mapped topic