SSI PoP

Patent metadata

Field	Value
Publication number	US-9773723-B2
Application number	US-201514958190-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	May 8, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

An assembly can include a first microelectronic package and a circuit structure comprising a plurality of dielectric layers and electrically conductive features thereon. The first package can include a substrate having a plurality of first contacts at a first or second surface thereof and a plurality of second contacts at the first surface thereof, and a first microelectronic element having a plurality of element contacts at a front surface thereof. The first contacts can be electrically coupled with the element contacts of the first microelectronic element. The electrically conductive features of the first circuit structure can include a plurality of bumps at the first surface of the circuit structure facing the second contacts of the substrate and joined thereto, a plurality of circuit structure contacts at a second surface of the circuit structure, and a plurality of traces coupling at least some of the bumps with the circuit structure contacts.

First claim

The invention claimed is:

1. An assembly, comprising:
a first microelectronic package, including a substrate having a plurality of first contacts at a first or second surface thereof and a plurality of second contacts at the first surface thereof, and a first microelectronic element having a plurality of element contacts at a front surface thereof, the first contacts electrically coupled with the element contacts of the first microelectronic element; and
a circuit structure having a first surface facing at least a portion of the first surface of the substrate with the first microelectronic element between the circuit structure and the substrate, the circuit structure comprising a plurality of dielectric layers and electrically conductive features therein, the circuit structure having a maximum thickness of less than 50 microns in a direction normal to the first surface of the circuit structure,
the electrically conductive features including a plurality of bumps at the first surface of the circuit structure facing the second contacts of the substrate and joined thereto, and a plurality of circuit structure contacts at a second surface of the circuit structure opposite the first surface thereof configured for connection with contacts of a component external to the assembly, the electrically conductive features including a plurality of traces coupling at least some of the bumps with the circuit structure contacts,
wherein at least one of: the bumps, or connections between the bumps and the second contacts of the substrate comprises a bond material, the assembly further comprising an underfill mechanically reinforcing the connections between the bumps of the circuit structure and the second contacts, the underfill having a composition different from a composition of the substrate, and different from a composition of the circuit structure.

2. The assembly as claimed in claim 1 , wherein the component external to the assembly is a second microelectronic package having a second microelectronic element therein, and the contacts of the component are terminals at a surface of the second microelectronic package electrically coupled with element contacts of the second microelectronic element,
the assembly further comprising the second microelectronic package, the terminals of the second microelectronic package facing at least some of the circuit structure contacts and joined thereto.

3. The assembly as claimed in claim 2 , wherein the first microelectronic element is an application processor, and the second microelectronic element embodies a greater number of active devices to provide memory storage array function than any other function.

4. The assembly as claimed in claim 1 , wherein the component external to the assembly is a second microelectronic element, the assembly further comprising the second microelectronic element, the contacts of the second microelectronic element facing at least some of the circuit structure contacts and joined thereto.

5. The assembly as claimed in claim 4 , further comprising a third microelectronic element spaced apart from the second microelectronic element in a direction parallel to the first surface of the circuit structure, contacts of the third microelectronic element facing at least some of the circuit structure contacts and joined thereto.

6. The assembly as claimed in claim 1 , wherein the element contacts of the first microelectronic element are electrically coupled with a first subset of the first contacts of the substrate, and the first microelectronic package further includes a second microelectronic element having a plurality of element contacts at a front surface thereof electrically coupled with a second subset of the first contacts of the substrate.

7. The assembly as claimed in claim 1 , wherein at least some of the traces are disposed closer to the first surface of the circuit structure and have maximum widths greater than maximum widths of the traces that are disposed closer to the second surface of the circuit structure.

8. The assembly as claimed in claim 1 , wherein at least some of the traces have maximum widths less than two microns.

9. A system comprising the assembly according to claim 1 and one or more other electronic components electrically connected with the assembly.

10. An assembly, comprising:
a first microelectronic package, including a substrate having a plurality of first contacts at a first or second surface thereof and a plurality of second contacts at the first surface thereof, and a first microelectronic element having a plurality of element contacts at a front surface thereof, the first contacts electrically coupled with the element contacts of the first microelectronic element; and
a circuit structure having a first surface facing at least a portion of the first surface of the substrate with the first microelectronic element between the circuit structure and the substrate, the circuit structure comprising a plurality of dielectric layers and electrically conductive features therein, the circuit structure having a maximum thickness of less than 50 microns in a direction normal to the first surface of the circuit structure,
the electrically conductive features including a plurality of bumps at the first surface of the circuit structure facing the second contacts of the substrate and joined thereto, and a plurality of circuit structure contacts at a second surface of the circuit structure opposite the first surface thereof configured for connection with contacts of a component external to the assembly, the electrically conductive features including a plurality of traces coupling at least some of the bumps with the circuit structure contacts,
wherein the bumps comprise extruded wire segments, the assembly further comprising a compliant underfill disposed between the first surface of the substrate and the second surface of the circuit structure, the underfill having a composition different from a composition of the substrate, and different from a composition of the circuit structure.

Assignees

• Invensas Corp

Inventors

• Haba Belgacem

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/951

  Materials of bond pads · CPC title

• H10W90/00

  Package configurations · CPC title