Compact semiconductor package and related methods

Patent metadata

Field	Value
Publication number	US-9257396-B2
Application number	US-201414284969-A
Country	US
Kind code	B2
Filing date	May 22, 2014
Priority date	May 22, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.

First claim

What is claimed is:

1. A method of forming a semiconductor package, comprising:
providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;
attaching a first die within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and
forming one or more interconnect lines spaced from the second surface and coupling the first die to at least one of the one or more conductive elements and to at least a conductive via through the first die.

2. The method of claim 1 , wherein the forming the one or more interconnect lines includes wire bonding the first die to the at least one of the one or more conductive elements.

3. The method of claim 1 , further comprising:
attaching a second die within the first one of the one or more substrate regions at the second surface; and
coupling the second die to the at least one of the one or more conductive elements.

4. The method of claim 1 , further comprising:
stacking a second die on the first die within the first one of the one or more substrate regions at the second surface, wherein the second die is electrically coupled to the first die; and
coupling the second die to the at least one of the one or more conductive elements.

5. The method of claim 1 , wherein one or more of the one or more conductive elements are electrically isolated and configured to function as a thermal conduction path.

6. A method of forming a semiconductor package, comprising:
providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;
attaching a first die within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and
coupling the first die to at least one of the one or more conductive elements;
wherein providing the substrate including the one or more conductive elements disposed therein comprises:
providing the substrate such that the one or more conductive elements extend from the first surface of the substrate and span part of a distance toward the second surface of the substrate opposite the first surface; and then
performing an etch process of the second surface of the substrate to expose the one or more conductive elements and thereby form the one or more substrate regions at the second surface.

7. A method of forming a semiconductor package, comprising:
providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;
depositing a first dielectric layer over the second surface of the substrate and the one or more conductive elements;
attaching a first die to the first dielectric layer within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and
coupling the first die to at least one of the one or more conductive elements.

8. The method of claim 7 , further comprising:
prior to coupling the first die to at least one of the one or more conductive elements, depositing a second dielectric layer over the second surface of the substrate; and
performing an etch process of the second surface of the substrate to expose an end portion of the at least one of the one or more conductive elements, wherein the exposed end portion of the at least one of the one or more conductive elements is then coupled to the first die.

9. The method of claim 8 , further comprising:
prior to coupling the first die to at least one of the one or more conductive elements, removing the second dielectric layer to expose the first die.

10. A method of forming a semiconductor package, comprising:
providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;
attaching a first die within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and
coupling the first die to at least one of the one or more conductive elements and to at least a conductive via through the first die;
wherein coupling the first die to the at least one of the one or more conductive elements comprises forming a first redistribution layer (RDL) over the first die, wherein the first RDL couples the first die to the at least one of the one or more conductive elements.

11. The method of claim 10 , further comprising:
prior to forming the first RDL, forming a dielectric layer over the first die; and
forming the first RDL over the dielectric layer.

12. The method of claim 11 , wherein a first set of electrically conductive paths penetrate the dielectric layer and electrically couple the first RDL to the first die.

13. The method of claim 10 , further comprising:
attaching a second die to an exposed outer surface of the first RDL, wherein the second die is electrically coupled to the first RDL, and wherein the second die is electrically coupled to the first die through the first RDL.

14. The method of claim 10 , further comprising forming a second RDL over the first surface of the substrate, wherein the second RDL is electrically coupled to the at least one of the one or more conductive elements.

15. A method of forming a compact integrated circuit package, comprising:
forming one or more electrically conductive structures each of which has a first end and a second end, the one or more electrically conductive structures formed within a substrate having a first surface and a second surface opposite the first surface, wherein the second end of each of the one or more electrically conductive structures is exposed and extends beyond the second surface of the substrate to demarcate one or more substrate regions at the second surface not occupied by the one or more electrically conductive structures;
inserting a first die within one of the one or more substrate regions at the second surface not occupied by the one or more electrically conductive structures; and
forming a first redistribution layer (RDL) over the second surface of the substrate and thereby embedding the first die, wherein the first RDL is coupled to the exposed second end of at least one of the one or more electrically conductive

Assignees

• Invensas Corp

Inventors

• Uzoh Cyprian Emeka

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title