Devices and Methods of Packaging Semiconductor Devices

Patent metadata

Field	Value
Publication number	US-2016190098-A1
Application number	US-201414584741-A
Country	US
Kind code	A1
Filing date	Dec 29, 2014
Priority date	Dec 29, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first semiconductor device and a second semiconductor device coupled to the first semiconductor device. An underfill material is disposed between the first semiconductor device and the second semiconductor device. The underfill material is also disposed on sidewalls of the first semiconductor device and the second semiconductor device. The underfill material has a first thickness on sidewalls of the first semiconductor device and a second thickness on sidewalls of the second semiconductor device. The second thickness is different than the first thickness.

First claim

1 - 9 . (canceled)

10 . A method of packaging a semiconductor device, the method comprising:
providing a fan-out structure having a first plurality of electrodes; providing a packaged semiconductor device having a second plurality of electrodes; aligning the first and second plurality of electrodes; coupling the packaged semiconductor device to the fan-out structure by their respective electrodes using a plurality of connectors; partially singulating the coupled packaged semiconductor device and fan-out structure along scribe lines disposed proximate sidewalls of the packaged semiconductor device and sidewalls of the fan-out structure; disposing an underfill material between the packaged semiconductor device and the fan-out structure and along the partially singulated scribe lines; and fully singulating the coupled packaged semiconductor device and fan-out structure along the scribe lines to form a packaged semiconductor device.

11 . The method according to claim 10 , wherein fully singulating the coupled packaged semiconductor device and fan-out structure comprises leaving a portion of the underfill material on sidewalls of the fan-out structure, sidewalls of the packaged semiconductor device, or sidewalls of both the fan-out structure and the packaged semiconductor device.

12 . The method according to claim 10 , wherein providing the fan-out structure comprises providing a wafer comprising a plurality of fan-out structures; wherein the method further comprises coupling the wafer to a first carrier, coupling a plurality of the packaged semiconductor devices to a second carrier, and coupling each of the plurality of the packaged semiconductor devices to one of the plurality of fan-out structures on the wafer using a plurality of connectors; wherein partially singulating the coupled packaged semiconductor device and fan-out structure comprises partially singulating the coupled plurality of the packaged semiconductor devices and plurality of fan-out structure along scribe lines disposed between adjacent plurality of packaged semiconductor devices and adjacent plurality of fan-out structures; wherein disposing the underfill material between the packaged semiconductor device and the fan-out structure comprises disposing the underfill material between the coupled plurality of packaged semiconductor devices and plurality of fan-out structures along the scribe lines; and wherein fully singulating the coupled packaged semiconductor device and the fan-out structure along the scribe lines comprises fully singulating the plurality of packaged semiconductor devices and the plurality of fan-out structures along the scribe lines to form a plurality of packaged semiconductor devices.

13 . The method according to claim 12 , further comprising removing the second carrier, before partially singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures; and removing the first carrier, after fully singulating the coupled plurality of packaged semiconductor device and the plurality of fan-out structures.

14 . The method according to claim 13 , wherein partially singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures comprises partially singulating the plurality of fan-out structures on the wafer.

15 . The method according to claim 14 , wherein fully singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures comprises leaving a portion of the underfill material on sidewalls of the plurality of packaged semiconductor devices and on an upper portion of sidewalls of the plurality of fan-out structures.

16 . The method according to claim 12 , further comprising removing the first carrier, before partially singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures; and removing the second carrier, after fully singulating the coupled plurality of packaged semiconductor device and the plurality of fan-out structures.

17 . The method according to claim 16 , wherein partially singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures comprises fully singulating the plurality of fan-out structures on the wafer.

18 . The method according to claim 16 , wherein fully singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures comprises leaving a portion of the underfill material on sidewalls of the plurality of fan-out structures and sidewalls of the plurality of packaged semiconductor devices.

19 . The method according to claim 12 , wherein the first carrier or the second carrier comprises a carrier tape or a carrier wafer.

20 . The method according to claim 12 , wherein partially singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures along the scribe lines comprises using a first saw blade, the first saw blade having a first width, wherein fully singulating the coupled plurality of packaged semiconductor devices and plurality of fan-out structures along the scribe lines comprises using a second saw blade, the second saw blade having a second width, and wherein the second width is less than the first width.

21 . A method of packaging a semiconductor device, the method comprising:
coupling a first plurality of packaged semiconductor devices to a wafer comprising a second plurality of packaged semiconductor devices formed therein; forming a plurality of recesses in the wafer, a respective one of the plurality of recesses disposed between adjacent ones of the second plurality of packaged semiconductor devices; filling the plurality of recesses with a non-conductive underfill material, the underfill material laterally surrounding each of the first plurality of packaged semiconductor devices; and singulating the wafer along the plurality of recesses to form a third plurality of packaged semiconductor devices, a respective one of the third plurality of packaged semiconductor devices comprising a respective one of the first plurality of packaged semiconductor devices and a respective one of the second plurality of packaged semiconductor devices.

22 . The method of claim 21 , wherein the coupling the first plurality of packaged semiconductor devices to the wafer comprises:
bonding a first surface of each of the first plurality of packaged semiconductor devices to a carrier; coupling a second surface of each the first plurality of packaged semiconductor devices to the wafer using a plurality of electrical connectors; and after the coupling, removing the carrier from the first surface of each of the first plurality of packaged semiconductor devices.

23 . The method of claim 21 , wherein the forming the plurality of recesses in the wafer comprises partially singulating the wafer along scribe lines disposed proximate between adjacent ones of the second plurality of packaged semiconductor devices.

24 . The method of claim 21 , wherein the plurality of recesses extend through a molding compound disposed between adjacent ones of the second plurality of packaged semiconductor devices.

25 . The method of claim 21 , wherein the underfill material remains disposed at sidewalls of each of the third plurality of packaged semiconductor devices.

26 . A method of packaging a semiconductor device, the method comprising:
bonding a first plurality of packaged semiconductor devices to a first redistribution layer (RDL) disposed over a first surface of a molding compound, the molding com

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Jie
• Chen Hsien-Wei

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title