Receiving circuit
US-9344269-B2 · May 17, 2016 · US
Referenceless and masterless global clock generator with a phase rotator-based parallel clock data recovery
US9768789B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9768789-B2 |
| Application number | US-201415110912-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 5, 2014 |
| Priority date | Feb 5, 2014 |
| Publication date | Sep 19, 2017 |
| Grant date | Sep 19, 2017 |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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- CPC / IPC classifications
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- Citations and related patents
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Abstract
Official abstract text for this publication.
The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.
First claim
Opening claim text (preview).
The invention claimed is: 1. The CDR (Clock Data Recovery) device, comprising: at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator, and wherein the global clock generator provides the frequency locked clock to a phase rotator included in each of the at least one or more CDR channels. 2. The CDR device of claim 1 , wherein the at least one or more CDR channels operate independently without requiring a master channel. 3. A CDR (Clock Data Recovery) device, comprising: at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator, and wherein a clock divider included in each of the at least one or more CDR channels creates the reference clock signal for each of at least one or more frequency detectors of the global clock generator. 4. A CDR (Clock Data Recovery) device, comprising: at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator, wherein the global clock generator includes at least one or more frequency detectors corresponding to the at least one or more CDR channels, and wherein the global clock generator includes: a frequency locked loop (FLL) digital loop filter configured to combine and accumulate outputs of the at least one or more frequency detectors; and a global VCO configured to generate the frequency locked clock based on an output of the FLL digital loop filter. 5. A global clock generator of a CDR (Clock Data Recovery) device, comprising: at least one or more frequency detectors configured to receive a reference clock signal from each of at least one or more CDR channels; a global VCO configured to provide a frequency locked clock to each of the at least one or more CDR channels based on an output of the at least one or more frequency detectors; and a frequency locked loop (FLL) digital loop filter configured to combine and accumulate outputs of the at least one or more frequency detectors. 6. The global clock generator of claim 5 , wherein each of the at least one or more frequency detectors corresponds to each of the at least one or more CDR channels. 7. The global clock generator of claim 5 , wherein the at least one or more CDR channels operate independently without requiring a master channel. 8. A global clock generator of a CDR (Clock Data Recovery) device, comprising: at least one or more frequency detectors configured to receive a reference clock signal from each of at least one or more CDR channels; and a global VCO configured to provide a frequency locked clock to each of the at least one or more CDR channels based on an output of the at least one or more frequency detectors, wherein the global VCO provides the frequency locked clock to a phase rotator included in each of the at least one or more CDR channels. 9. A global clock generator of a CDR (Clock Data Recovery) device, comprising: at least one or more frequency detectors configured to receive a reference clock signal from each of at least one or more CDR channels; a global VCO configured to provide a frequency locked clock to each of the at least one or more CDR channels based on an output of the at least one or more frequency detectors; and a clock divider configured to divide the frequency locked clock and to provide the divided frequency locked clock to the at least one or more frequency detectors.
Assignees
Inventors
Classifications
using frequency discriminator · CPC title
the phase shifting device being digitally controlled · CPC title
provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title
- H03L7/0807Primary
concerning mainly a recovery circuit for the reference signal · CPC title
using several loops, e.g. for redundant clock signal generation · CPC title
Patent family
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9768789B2 cover?
- The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.
- Who is the assignee on this patent?
- Korea Advanced Inst Sci & Tech, Korea Advanced Insitute Of Science And Tech
- What technology area does this patent fall under?
- Primary CPC classification H03L7/0807. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).