Receiving circuit

Patent metadata

Field	Value
Publication number	US-9344269-B2
Application number	US-201514681794-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	May 30, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A receiving circuit includes circuits arranged in parallel, each circuits including a voltage-controlled-oscillator (VCO) configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, and a gain circuit. Each circuit is configured to sample a piece of input data with an output clock of the VCO and adjust the oscillation frequency of the VCO based on a phase difference and a frequency difference between the piece of input data and the output clock, thereby recovering data and a clock based on the piece of input data. The gain circuit is configured to adjust ratios of gains of up and down of the oscillation frequency of the VCO in a loop in each circuit arranged adjacent to each other, based on a phase difference between the pieces of input data and a phase difference between the output clocks of the respective circuits.

First claim

What is claimed is:

1. A receiving circuit comprising:
a plurality of clock-and-data recovery circuits arranged in parallel, each clock-and-data recovery circuit including an LC voltage controlled oscillator configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, and each clock-and-data recovery circuit being configured to sample a piece of input data with an output clock of the LC voltage controlled oscillator and adjust the oscillation frequency of the LC voltage controlled oscillator in accordance with a phase difference and a frequency difference between the piece of input data and the output clock of the LC voltage controlled oscillator, thereby recovering data and a clock based on the piece of input data; and
a gain adjustment circuit configured to adjust ratios of gains of up and down of the oscillation frequency of the LC voltage controlled oscillator in a loop in each of the clock-and-data recovery circuits arranged adjacent to each other, in accordance with a phase difference between the pieces of input data and a phase difference between the output clocks of the respective clock-and-data recovery circuits.

2. The receiving circuit according to claim 1 , wherein the gain adjustment circuit is further configured to include:
a first phase detector circuit configured to detect the phase difference between the pieces of input data;
a second phase detector circuit configured to detect the phase difference between the output clocks; and
a phase difference calculation circuit configured to adjust the gains in the loop in each of the clock-and-data recovery circuit, in accordance with a difference between the phase difference between the pieces of input data and the phase difference between the output clocks, based on results of the detection of the first phase detector circuit and the second phase detector circuit.

3. The receiving circuit according to claim 2 ,
wherein the first phase detector circuit is further configured to include a third phase detector circuit configured to detect a phase difference between a reference clock and a corresponding piece of input data in each of the clock-and-data recovery circuits arranged adjacent to each other and a fourth phase detector circuit configured to detect a phase difference between the reference clock and a corresponding piece of input data in each of the clock-and-data recovery circuits arranged adjacent to each other,
wherein the second phase detector circuit is further configured to include a fifth phase detector circuit configured to detect a phase difference between the reference clock and a corresponding output clock in each of the clock-and-data recovery circuits arranged adjacent to each other and a sixth phase detector circuit configured to detect a phase difference between the reference clock and a corresponding output clock in each of the clock-and-data recovery circuits arranged adjacent to each other.

4. The receiving circuit according to claim 3 , further comprising:
a phase interpolation circuit configured to generate a clock based on the output clock of each of the clock-and-data recovery circuits arranged adjacent to each other, and output the generated clock as the reference clock.

5. The receiving circuit according to claim 2 , wherein
the piece of input data and the output clock of each of the clock-and-data recovery circuits are frequency-divided, and
the first phase detector circuit and the second phase detector circuit detect the phase difference between the pieces of input data and the phase difference between the output clocks by use of the frequency-divided pieces of input data and output clocks.

6. The receiving circuit according to claim 5 , wherein frequency division ratios for the pieces of input data and the output clocks are set such that the gains of the first phase detector circuit and the second phase detector circuit are equalized.

7. The receiving circuit according to claim 2 , wherein a weight on the phase difference between the pieces of input data and a weight on the phase difference between the output clocks are set such that the gains of the first phase detector circuit and the second phase detector circuit are equalized.

8. The receiving circuit according to claim 1 ,
wherein each of the clock-and-data recovery circuits is further configured to include:
a phase-frequency detector circuit configured to detect a phase difference and a frequency difference between the piece of input data and the output clock of the LC voltage controlled oscillator; and
a control circuit configured to supply the LC voltage controlled oscillator with a control signal used to control the oscillation frequency of the LC voltage controlled oscillator, and
wherein the control circuit outputs the control signal according to a result of the detection of the phase-frequency detector circuit and an output of the gain adjustment circuit.

9. The receiving circuit according to claim 8 , wherein the control circuit is further configured to include:
a charge pump circuit configured to perform an addition or subtraction of a current on the control signal in accordance with the result of the detection of the phase-frequency detector circuit and the output of the gain adjustment circuit; and
a filter configured to filter a high-frequency component of an output of the charge pump circuit.

10. The receiving circuit according to claim 8 , wherein the control circuit is further configured to include:
a digital filter configured to generate the control signal by performing digital signal processing on the result of the detection of the phase-frequency detector circuit and the output of the gain adjustment circuit.

Assignees

• Fujitsu Ltd

Inventors

• Shibasaki Takayuki

Classifications

• H03B5/1212

  the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title