Self aligned via in integrated circuit

Patent metadata

Field	Value
Publication number	US-9768113-B2
Application number	US-201615152981-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	Jun 24, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

First claim

What is claimed is:

1. A method for forming a via in an integrated circuit, the method comprising:
patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer;
removing an exposed portion of the first OPL layer to define a cavity;
removing an exposed portion of a second hardmask disposed under the first OPL layer to further define the cavity;
removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity;
removing an exposed portion of a first cap layer disposed under the first dielectric layer to further define the cavity;
removing an exposed portion of a second dielectric layer disposed under the first cap layer to further define to further define the cavity;
removing an exposed portion of a second cap layer disposed under the second dielectric layer to further define to further define the cavity;
removing an exposed portion of a liner layer over a second conductive material in the cavity; and
depositing a conductive material in the cavity.

2. The method of claim 1 , further comprising depositing a single layer of liner material in the cavity prior to depositing a conductive material in the cavity.

3. The method of claim 1 , wherein the first hardmask includes a titanium nitride (TiN) layer and an oxide material layer disposed between the TiN layer and the first OPL layer.

4. The method of claim 1 , wherein the removing the exposed portion of the first OPL layer to define a cavity is performed by a reactive ion etching (RIE) process that is selective to TiN material.

5. The method of claim 1 , wherein the removing the exposed portion of the first OPL layer to define a cavity is performed by a reactive ion etching (RIE) process that is selective to TiN and oxide materials.

6. The method of claim 1 , wherein the second hardmask includes an oxide material.

7. The method of claim 1 , wherein the second hardmask includes a nitride material.

8. The method of claim 1 , wherein the second cap layer is a nitride.

9. The method of claim 8 , wherein the nitride is chosen from the group consisting of silicon nitride, silicon carbon nitride, or silicon oxynitride.

10. The method of claim 1 , wherein the second cap layer is an oxide.

11. The method of claim 1 , wherein the second cap layer is a silicon oxide.

Assignees

• IBM
• Tokyo Electron Ltd
• St Microelectronics Inc

Inventors

• Feurprier Yannick
• Lee Joe
• Liebmann Lars W
• Mignot Yann
• Spooner Terry A
• Trickett Douglas M
• Yilmaz Mehmet

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/287

  by chemical means · CPC title