Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9768025-B2
Application number	US-201615184491-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Nov 2, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method of fabricating a semiconductor device includes forming a target layer on a substrate, forming a plurality of reference patterns at uniform intervals on the target layer, forming a plurality of spacers on the side surfaces of the reference patterns, forming a plurality of filling patterns in spaces left between the spacers, forming a surface-modified filling pattern by performing a first surface treatment on a portion of the plurality of filling patterns, forming a surface-modified reference pattern by performing a second surface treatment on a portion of the plurality of reference patterns, and removing the plurality of filling patterns and the plurality of reference patterns and leaving the surface-modified filling pattern and the surface-modified reference pattern on the target layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a target layer on a substrate;
forming a plurality of reference patterns on the target layer, wherein the reference patterns are spaced at uniform intervals from one another;
forming a plurality of spacers covering both side surfaces of each of the reference patterns;
forming a plurality of filling patterns filling spaces between the spacers;
performing a first surface treatment on a portion of the plurality of filling patterns to form a surface-modified filling pattern;
performing a second surface treatment on a portion of the plurality of reference patterns to form a surface-modified reference pattern; and
removing the plurality of filling patterns and the plurality of reference patterns without removing the surface-modified filling pattern and the surface-modified reference pattern.

2. The method according to claim 1 , wherein the forming of the surface-modified filling pattern comprises:
forming a first mask covering the plurality of filling patterns, the plurality of spacers, and the plurality of reference patterns, the first mask having a first opening which exposes the portion of the plurality of filling patterns; and
densifying at least an upper part of the portion of the plurality of filling patterns exposed by the first opening.

3. The method according to claim 1 , wherein the first surface treatment is an ion implantation process comprising implanting silicon (Si), germanium (Ge), or metal ions into the portion of the plurality of filling patterns exposed by the first opening.

4. The method according to claim 1 , wherein the first surface treatment is a plasma process of forming a plasma from at least one of argon (Ar), nitrogen (N 2 ), helium (He), krypton (Kr), and xenon (Xe), and subjecting the portion of the plurality of filling patterns exposed by the first opening to the plasma.

5. The method according to claim 1 , wherein the plurality of filling patterns comprises a spin on hardmask (SOH) or an amorphous carbon layer (ACL), and
the surface-modified filling pattern comprises a densified SOH or a densified ACL.

6. The method according to claim 5 , wherein the surface-modified filling pattern comprises a densified SOH or a densified ACL comprising silicon (Si), germanium (Ge), or metal atoms.

7. The method according to claim 1 , wherein the surface-modified filling pattern has an etch selectivity with respect to the plurality of filling patterns.

8. The method according to claim 1 , wherein the forming of the surface-modified reference pattern comprises:
forming a second mask covering the plurality of filling patterns, the plurality of spacers, and the plurality of reference patterns, the second mask having a second opening which exposes the portion of the plurality of reference patterns; and
nitriding the portion of the plurality of reference patterns exposed by the second opening.

9. The method according to claim 1 , wherein the second surface treatment is a plasma process comprising forming a plasma from at least one of ammonia (NH 3 ), nitrogen oxide (N 2 O), oxygen (O 2 ), and carbon monoxide (CO), and subjecting the portion of the plurality of reference patterns exposed by the second opening to the plasma.

10. The method according to claim 1 , wherein the second surface treatment is an ion implantation process comprising implanting nitrogen ions into the portion of the plurality of reference patterns exposed by the second opening.

11. The method according to claim 1 , wherein the plurality of reference patterns comprise amorphous silicon, and
the surface-modified reference pattern comprises silicon nitride or silicon oxynitride.

12. The method according to claim 1 , wherein the surface-modified reference pattern has an etch selectivity with respect to the plurality of reference patterns.

13. The method according to claim 1 , wherein the removing of the plurality of filling patterns and the plurality of reference patterns comprises:
removing the plurality of filling patterns without removing the surface-modified filling pattern, the surface-modified reference pattern, and the plurality of spacers,
by a separate process, removing the plurality of reference patterns without removing the surface-modified filling pattern, the surface-modified reference pattern, and the plurality of spacers.

14. The method according to claim 1 , wherein, in the removing of the plurality of filling patterns and the plurality of reference patterns, an upper surface of the target layer is exposed,
the method further comprising:
forming a target layer pattern by patterning the target layer using the plurality of spacers, the surface-modified filling pattern, and the surface-modified reference pattern as an etch mask.

15. The method according to claim 14 , wherein the target layer pattern has a first line pattern space and a second line pattern space which are spaced apart from each other by a first line separation pattern, and a first line pattern space and a second line pattern space which are spaced apart from each other by a second line separation pattern.

16. The method according to claim 15 , wherein the first line pattern space and the second line pattern space which are spaced apart by the first line separation pattern are both located in a first region of the target layer pattern located, as viewed in plan, between side surfaces of two neighboring ones of the spacers, and
the first line pattern space and the second line pattern space which are spaced apart by the second line separation pattern are both located in a second region of the target layer pattern located, as viewed in plan, between side surfaces of two neighboring ones of the spacers.

17. The method according to claim 16 , wherein, in the forming of the target layer pattern, the first and second line separation patterns are formed in portions of the target layer covered by the surface-modified filling pattern and the surface-modified reference pattern, respectively.

18. A method of fabricating a semiconductor device, the method comprising:
forming a plurality of reference patterns on an upper surface of an etch target, wherein the reference patterns are spaced apart from each other in a first direction parallel to the upper surface of the etch target and such that each of the reference patterns has opposite side surfaces in the first direction;
forming a plurality of spacers on the plurality of reference patterns, wherein the spacers cover the side surfaces of the reference patterns, respectively, and such that spaces are left between respective ones of the spacers adjacent to one another in the first direction;
forming a plurality of filling patterns in the spaces between said respective ones of the spacers such that a respective pair of the spacers is located on opposite sides of each of the filling patterns in the first direction;
selectively treating one portion of said filling and reference patterns to form at least one modified pattern spanning respective parts of two of the spacers adjacent to each other in the first direction;
removing a portion of the filling patterns and the reference patterns which was not treated to form said at least one modified pattern, without removing the spacers and each said at least one modified pattern; and
subsequently etching the etch target using the spacers and each said at least one modified pattern together as an etch mask.

19. The method according to claim 18 , wherein the selective treating of said on

Assignees

• Siew Yongkong
• Jung Sung-Yup
• Samsung Electronics Co Ltd

Inventors

• Siew Yongkong
• Jung Sung-Yup

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P76/4088 Primary

  Processes for improving the resolution of the masks · CPC title