Clock source, method for distributing a clock signal and integrated circuit

Patent metadata

Field	Value
Publication number	US-9766651-B2
Application number	US-201314651279-A
Country	US
Kind code	B2
Filing date	Jan 8, 2013
Priority date	Jan 8, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.

First claim

The invention claimed is:

1. A distributed clock signal generator in or for an integrated circuit, the distributed clock signal generator comprising:
a primary oscillator configured to generate a primary clock signal based on a reference control signal;
at least one secondary oscillator wherein each secondary oscillator is configured to generate a secondary clock signal based on the reference control signal;
wherein for each secondary oscillator a frequency correction unit is provided and configured such to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal; and
wherein each frequency correction unit comprises an integrator which is adapted to integrate the primary clock signal and to integrate the secondary clock signal of the associated secondary oscillator and wherein each frequency correction unit is adapted to adjust the reference control signal for the associated secondary oscillator based on the difference between the integrated primary clock signal and the integrated respective secondary clock signal.

2. The distributed clock signal generator according to claim 1 ,
wherein the integrator comprises a first counter adapted to count the clock cycles of the primary clock signal and a second counter adapted to count the clock cycles of the secondary clock signal of the associated secondary oscillator.

3. The distributed clock signal generator according to claim 1 ,
wherein each frequency correction unit is adapted to integrate the primary clock signal and the secondary clock signal of the associated secondary oscillator over a predefined time interval and to provide the adjusted reference control signal after every time interval.

4. The distributed clock signal generator according to claim 3
wherein the time interval lasts longer than a period duration of the frequency of the primary clock signal.

5. The distributed clock signal generator according to claim 1 ,
wherein each frequency correction unit comprises a comparator adapted to calculate the difference between the integrated primary clock signal and the integrated secondary clock signal of the associated secondary oscillator.

6. The distributed clock signal generator according to claim 5 ,
wherein each frequency correction unit comprises a converter adapted to convert the difference into an analogue correction signal.

7. The distributed clock signal generator according to claim 6 ,
wherein each frequency correction unit comprises an adder adapted to add the analogue correction signal to the reference control signal and wherein each frequency correction unit is adapted to output the adjusted reference control signal to the associated secondary oscillator.

8. The distributed clock signal generator according to claim 1 , wherein the primary oscillator is a component of a phase locked loop of the integrated circuit.

9. The distributed clock signal generator according to claim 1 ,
wherein the integrated circuit comprises a controlled current source adapted to generate the reference control signal according to a predetermined frequency of the primary clock signal; and
wherein the reference control signal comprises a control current.

10. The distributed clock signal generator according to claim 9 ,
wherein the predetermined frequency of the primary clock signal is in a frequency range between 1 MHz and 10 GHz.

11. The distributed clock signal generator according to claim 1 ,
wherein the primary oscillator and the secondary oscillators are current controlled oscillators; and/or
wherein the primary oscillator and the secondary oscillators have an identical electrical and/or geometrical structure.

12. An integrated circuit, comprising:
at least one distributed clock signal generator for providing a primary clock signal and at least one secondary clock signal, the distributed clock signal generator comprising:
a primary oscillator configured to generate a primary clock signal based on a reference control signal;
at least one secondary oscillator wherein each secondary oscillator is configured to generate a secondary clock signal based on the reference control signal;
wherein for each secondary oscillator, a frequency correction unit is provided wherein each frequency correction unit comprises an integrator which is adapted to integrate the primary clock signal and to integrate the secondary clock signal of the associated secondary oscillator and wherein each frequency correction unit is adapted to adjust the reference control signal for the associated secondary oscillator based on the difference between the integrated primary clock signal and the integrated respective secondary clock signal and such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal;
at least one primary logic unit which is supplied with the primary clock signal;
at least one secondary logic unit which is supplied with the secondary clock signals.

13. The integrated circuit of claim 12 ,
wherein the primary logic unit and the at least one secondary logic unit are remotely located on the substrate of the integrated circuit; and/or
wherein each secondary oscillator is located near the associated secondary logic unit.

14. The integrated circuit claim 12 ,
wherein the primary logic unit and the at least one secondary logic unit are distanced to each other, wherein a distance between the primary logic unit and the at least one secondary logic unit is greater than 5 mm.

15. The integrated circuit of claim 12 , comprising a reference current source adapted to generate the reference control signal based on a predetermined frequency of the primary clock signal.

16. A method for distributing a clock signal for integrated circuits, comprising:
providing a primary oscillator and at least one secondary oscillator;
generating by the primary oscillator a primary clock signal based on a reference control signal;
generating by the at least one secondary oscillator a secondary clock signal based on the reference control signal;
increasing or decreasing the reference control signal of the at least one secondary oscillator based on a difference of the primary clock signal and the secondary clock signal of the respective secondary oscillator such that the clock frequency of the respective secondary clock signal essentially equals the clock frequency of the primary clock signal;
integrating the primary clock signal;
integrating the secondary clock signal of the secondary oscillator, and
adjusting the reference control signal for the associated secondary oscillator based on the difference between the integrated primary clock signal and the integrated respective secondary clock signal.

17. The integrated circuit of claim 12 , wherein the integrator comprises a first counter adapted to count the clock cycles of the primary clock signal and a second counter adapted to count the clock cycles of the secondary clock signal of the associated secondary oscillator.

Assignees

• Priel Michael
• Kuzmin Dan
• Sofer Sergey
• Nxp Usa Inc

Inventors

• Priel Michael
• Kuzmin Dan
• Sofer Sergey

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title