Increasing PWM resolution for digitally controlled motor control applications

Patent metadata

Field	Value
Publication number	US-9762174-B2
Application number	US-201514972515-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Feb 9, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Systems and methods for increasing Pulse Width Modulation (PWM) resolution for digitally controlled motor control applications are described. For example, in some embodiments, a method may include receiving a clock signal having a given period; identifying a target duty cycle; calculating a comparison point based upon the given period and the target duty cycle; generating a PWM signal based upon the clock signal using the comparison point; and varying the comparison point to increase a resolution of an effective duty cycle of the PWM signal.

First claim

The invention claimed is:

1. A method, comprising:
receiving a clock signal having a frequency;
selecting a target duty cycle for a Pulse-Width Modulated (PWM) signal and a target PWM frequency for the PWM signal;
determining multiple different comparison points based on the frequency of the clock signal, the target duty cycle for the PWM signal, and the target PWM frequency, each of the comparison points being determined based on the target duty cycle for the PWM signal; and
generating the PWM signal based on the clock signal, the target duty cycle, and the comparison points such that different comparison points are used in different PWM periods for at least two consecutive PWM periods of the PWM signal.

2. The method of claim 1 , wherein the multiple comparison points include a first comparison point and a second comparison point, and wherein generating the PWM signal includes:
generating the PWM signal using the first comparison point during a first period of the PWM signal; and
generating the PWM signal using the second comparison point during a second period of the PWM signal immediately following the first period of the PWM signal.

3. The method of claim 1 , further comprising, in response to an accumulated duty cycle of the PWM signal being smaller than the target duty cycle, increasing a comparison point for a subsequent period.

4. The method of claim 1 , further comprising, in response to an accumulated duty cycle of the PWM signal being greater than or equal to the target duty cycle, using an original value of a calculated comparison point for a subsequent period.

5. The method of claim 1 , wherein an average difference between an accumulated duty cycle of the PWM signal and the target duty cycle over a selected number of cycles is zero.

6. The method of claim 5 , wherein the selected number of cycles is four, and wherein the method further includes periodically increasing a comparison count by 1 for a number of the selected number of cycles to produce an increased resolution corresponding to a quarter of a comparison count.

7. The method of claim 5 , wherein the selected number of cycles is five, and wherein the method further includes periodically increasing a comparison count by 1 for a number of the selected number of cycles to produce an increased resolution corresponding to a fifth of a comparison count.

8. The method of claim 1 , further comprising applying the PWM signal to a motor.

9. An electronic circuit, comprising:
a controller; and
a memory coupled to the controller, the memory having program instructions stored thereon that, upon execution by the controller, cause the controller to:
determine multiple different comparison points based on a frequency of a clock signal, a target duty cycle for a Pulse-Width Modulated (PWM) signal, and a target PWM frequency for the PWM signal, each of the comparison points being determined based on the target duty cycle for the PWM signal; and
generate the PWM signal based on the clock signal, the target duty cycle, and the comparison points such that different comparison points are used in different PWM periods for at least two consecutive PWM periods of the PWM signal.

10. The electronic circuit of claim 9 , wherein the program instructions, upon execution, further cause the controller to, in response to an accumulated duty cycle of the PWM signal being smaller than the target duty cycle, increase a current value of a comparison point for an immediately subsequent period.

11. The electronic circuit of claim 10 , wherein the program instructions, upon execution, further cause the controller to, in response to an accumulated duty cycle of the PWM signal being greater than the target duty cycle, decrease a current value of a comparison point for an immediately subsequent period.

12. The electronic circuit of claim 10 , wherein an average difference between an accumulated duty cycle of the PWM signal and the target duty cycle over a predetermined number of cycles is zero.

13. A device, comprising:
an electronic circuit configured to:
determine multiple different comparison points based on a frequency of a clock signal, a target duty cycle for a Pulse-Width Modulated (PWM) signal, and a target PWM frequency for the PWM signal, each of the comparison points being determined based on the target duty cycle for the PWM signal; and
generate the PWM signal based on the clock signal, the target duty cycle, and the comparison points such that different comparison points are used in different PWM periods for at least two consecutive PWM periods of the PWM signal, the device further comprising:

an electric motor coupled to the electronic circuit, the electric motor configured to be driven by the PWM signal.

14. The device of claim 13 , wherein the electronic circuit is further configured to, in response to an accumulated duty cycle of the PWM signal being smaller than the target duty cycle, increase a current value of a comparison count for an immediately subsequent period.

15. The device of claim 13 , wherein the electronic circuit is further configured to, in response to an accumulated duty cycle of the PWM signal being greater than the target duty cycle, decrease a current value of a comparison count for an immediately subsequent period.

16. The device of claim 13 , wherein an average difference between an accumulated duty cycle of the PWM signal and the target duty cycle over a predetermined number of periods is zero.

17. The device of claim 16 , wherein the predetermined number of cycles is N, and wherein the electronic circuit is further configured to increase a comparison count by 1 during one or more of the predetermined number of cycles to produce an increased resolution corresponding to a 1/N of a comparison count.

18. The device of claim 17 , wherein N is two, three, four, five, or six.

19. The device of claim 17 , wherein the electronic circuit is further configured to distribute the increase in comparison count uniformly over the predetermined number of cycles.

Assignees

• Texas Instruments Inc

Inventors

• Dalvi Jasraj R
• Oh Seil
• Rote John K

Classifications

• H02P27/085 Primary

  wherein the PWM mode is adapted on the running conditions of the motor, e.g. the switching frequency · CPC title

• H02P2209/09

  PWM with fixed limited number of pulses per period · CPC title