Pulse width modulation signal generation circuit and method

Patent metadata

Field	Value
Publication number	US-9531367-B2
Application number	US-201514960425-A
Country	US
Kind code	B2
Filing date	Dec 6, 2015
Priority date	Jan 14, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A pulse width modulation signal generation circuit and a pulse width modulation signal generation method are provided. A clock generator is configured for generating a clock signal including a plurality of pulses. The counting unit is coupled to the clock generator, and configured for storing a period parameter and outputting a counting value by counting the pulses of the clock signal based on the period parameter and a bidirectional counting mode. The comparing unit is coupled to the counting unit and is configured for comparing the counting value and a comparing threshold to output a level control signal. The signal generating unit is coupled to the comparing unit and configured for generating a pulse width modulation signal according to the level control signal. When the period parameter is odd, the counting value outputted by the counting unit is equal to a middle value in the two continuous clock cycles.

First claim

What is claimed is:

1. A pulse width modulation signal generation circuit, comprising:
a clock generator, generating a clock signal comprising a plurality of pulses;
a counting unit, coupled to the clock generator, storing a period parameter, and counting the pulses of the clock signal based on the period parameter and a bidirectional counting mode to output a counting value;
a comparing unit, coupled to the counting unit and comparing the counting value and a comparing threshold to output a level control signal accordingly; and
a signal generating unit, coupled to the comparing unit and generating a pulse width modulation signal based on the level control signal, wherein when the period parameter is an odd number, the counting value output by the counting unit is a middle value in two consecutive clock cycles.

2. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein when the period parameter is an even number, the counting value output by the counting unit is the middle value in one single clock cycle.

3. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein the period parameter is set as the number of pulses of the clock signal in a signal cycle of the pulse width modulation signal.

4. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein the middle value is a maximal integer not greater than an outcome of the period parameter divided by two.

5. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein when the period parameter is an odd number, the counting unit counts up in response to the clock signal to output the sequentially increasing counting value, keeps outputting the middle value for two consecutive clock cycles, and then counts down to output the sequentially decreasing counting value.

6. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein when the period parameter is an odd number, within one signal cycle of the pulse width modulation signal, the signal generating unit adjusts the pulse width modulation signal from a first level to a second level based on one of a positive edge and a negative edge of the clock signal, and adjusts the pulse width modulation signal from the second level to the first level based on the other one of the positive edge and the negative edge of the clock signal.

7. The pulse width modulation signal generation circuit as claimed in claim 6 , wherein when the period parameter is an odd number, a duty cycle of the pulse width modulation signal is 50%.

8. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein the counting unit further comprises:
a counter, coupled to the clock generator and outputting the counting value in response to the clock signal; and
a controller, coupled to the counter, receiving a comparison result generated by comparing the middle value and the counting value and an odd-even determining bit, controlling the counter to count up or down based on the comparison result, and determining whether the counter outputs the middle value in two consecutive clock cycles based on the odd-even determining bit.

9. The pulse width modulation signal generation circuit as claimed in claim 8 , wherein the counting unit further comprises:
a counting register, coupled to the controller and storing the period parameter, so as to output the middle value and the odd-even determining bit based on the period parameter; and
a first comparator, having a first input end, a second input end, and an output end, wherein the first input end of the first comparator is coupled to the counter to receive the counting value, the second input end of the first comparator is coupled to the counting register to receive the middle value, and the output end of the first comparator outputs the comparison result.

10. The pulse width modulation signal generation circuit as claimed in claim 8 , wherein the controller outputs a control signal to the signal generating unit based on the odd-even determining bit, so as to control the signal generating unit to adjust the level of the pulse width modulation signal in response to a positive or negative edge of the clock signal.

11. The pulse width modulation signal generation circuit as claimed in claim 1 , wherein the comparing unit comprises:
a second comparator, having a first input end, a second input end, and an output end, wherein the first input end of the second comparator is coupled to the counting unit to receive the counting value, the output end of the second comparator is coupled to the signal generating unit to output the level control signal to the signal generating unit; and
a comparing register, storing the comparing threshold and coupled to the second input end of the second comparator to output the comparing threshold to the second comparator.

12. A pulse width modulation signal generation method, comprising:
providing a period parameter and a comparing threshold, and receiving a clock signal comprising a plurality of pulses;
counting the clock signal based on the period parameter and a bidirectional counting mode, so as to output a counting value;
determining whether the period parameter is an odd number or an even number;
when the period parameter is an odd number and the counting value is increased to a middle value, outputting the counting value equal to the middle value in two consecutive clock cycles;
comparing the counting value and the comparing threshold to determine an output level of the pulse width modulation signal, and outputting the pulse width modulation signal.

13. The pulse width modulation signal generation method as claimed in claim 12 , further comprising:
when the period parameter is an even number, outputting the counting value equal to the middle value in one single clock cycle.

14. The pulse width modulation signal generation method as claimed in claim 12 , wherein the period parameter is set as the number of pulses of the clock signal in a signal cycle of the pulse width modulation signal.

15. The pulse width modulation signal generation method as claimed in claim 12 , wherein the middle value is a maximal integer not greater than an outcome of the period parameter divided by two.

16. The pulse width modulation signal generation method as claimed in claim 12 , wherein the step of counting the clock signal based on the period parameter and the bidirectional counting mode, so as to output the counting value, comprises:
during a counting up period in the bidirectional counting mode, counting up in response to the clock signal to output the sequentially increasing counting value until the counting value is equal to the middle value; and
during a counting down period in the bidirectional counting mode, counting down in response to the clock signal to output the sequentially decreasing counting value until the counting value becomes zero.

17. The pulse width modulation signal generation method as claimed in claim 12 , further comprising:
when the period parameter is an odd number, within one signal cycle of the pulse width modulation signal, adjusting the pulse width modulation signal from a first level to a second level based on one of a positive edge and a negative edge of the clock signal, and adjusting the pulse width modulation signal from the second level to the first level based on the other one of the positive edge and the negative edge of the clock signal.

18. The pulse width modulation signal generation method as claimed in claim 17 , wherein when the per

Assignees

• Nuvoton Technology Corp

Inventors

• Liu Ming-Ying

Classifications

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K21/023

  comprising pulse shaping or differentiating circuits · CPC title