Interconnect structure with twin boundaries and method for forming the same

Patent metadata

Field	Value
Publication number	US-9761523-B2
Application number	US-201514832055-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	Aug 21, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a substrate; and
a conductive structure formed over the substrate, wherein the conductive structure comprises twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

2. The semiconductor device structure as claimed in claim 1 , wherein the twin boundaries have an average twin-lamella width in a range from about 4 nm to about 40 nm.

3. The semiconductor device structure as claimed in claim 1 , wherein the conductive structure comprises:
a diffusion barrier layer; and
a conductive material formed over the diffusion barrier layer.

4. The semiconductor device structure as claimed in claim 1 , wherein a lattice mismatch ratio between a lattice constant of the diffusion barrier layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

5. The semiconductor device structure as claimed in claim 3 , further comprising:
a glue layer formed between the diffusion barrier layer and the conductive material, wherein a lattice mismatch ratio between a lattice constant of the glue layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

6. The semiconductor device structure as claimed in claim 4 , wherein the diffusion barrier layer is made of ruthenium (Ru), nickel (Ni), ∝-cobalt (Co), β-cobalt (Co), cobalt nitride (Co4N) or combinations thereof.

7. The semiconductor device structure as claimed in claim 1 , further comprising:
a via-trench structure formed over the conductive material, wherein the via-trench structure comprises twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

8. The semiconductor device structure as claimed in claim 1 , further comprising:
a device element formed in the substrate; and
a dielectric layer formed over the device element, wherein the conductive structure is electrically connected to the device element.

9. A semiconductor device structure, comprising:
a first dielectric layer formed over a substrate;
a diffusion barrier layer formed in the first dielectric layer; and
a conductive material formed over the diffusion barrier layer, wherein a lattice mismatch ratio between a lattice constant of the diffusion barrier layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

10. The semiconductor device structure as claimed in claim 9 , wherein the conductive structure comprises twin boundaries, and a density of the twin boundaries is a in a range from about 25 μm −1 to about 250 μm −1 .

11. The semiconductor device structure as claimed in claim 10 , wherein the twin boundaries have an average twin-lamella width in a range from about 4 nm to about 40 nm.

12. The semiconductor device structure as claimed in claim 9 , wherein the diffusion barrier layer is made of ruthenium (Ru), nickel (Ni), ∝-cobalt (Co), β-cobalt (Co), cobalt nitride (Co4N) or combinations thereof.

13. The semiconductor device structure as claimed in claim 9 , further comprising:
a glue layer formed between the diffusion barrier layer and the conductive material, wherein a lattice mismatch ratio between a lattice constant of the glue layer and a lattice constant of the conductive material is in a range from about 0.1% to about 6%.

14. The semiconductor device structure as claimed in claim 9 , further comprising:
a via-trench structure formed over the conductive material, wherein the via-trench structure comprises twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

15. A semiconductor device structure, comprising:
a first dielectric layer formed over a substrate;
a first diffusion barrier layer formed in the first dielectric layer;
a first conductive material formed over the first diffusion barrier layer; and
a via-trench structure formed over the conductive material, wherein the via-trench structure comprises twin boundaries, and a density of the twin boundaries is in a range from about 25 μm −1 to about 250 μm −1 .

16. The semiconductor device structure as claimed in claim 15 , wherein the via-trench structure comprises a second diffusion barrier layer and a second conductive material formed over the second diffusion barrier layer, and a lattice mismatch ratio between a lattice constant of the second diffusion barrier layer and a lattice constant of the second conductive material is in a range from about 0.1% to about 6%.

17. The semiconductor device structure as claimed in claim 16 , wherein the via-trench structure further comprises a second glue layer between the second diffusion barrier layer and the second conductive material.

18. The semiconductor device structure as claimed in claim 15 , further comprising:
an etch stop layer formed over the first dielectric layer; and
a capping layer formed in the etch stop layer, wherein the via-trench structure is formed over the capping layer and in direct contact with the capping layer.

19. The semiconductor device structure as claimed in claim 15 , further comprising:
a first glue layer formed between the first diffusion barrier layer and the first conductive material, wherein a lattice mismatch ratio between a lattice constant of the first glue layer and a lattice constant of the first conductive material is in a range from about 0.1% to about 6%.

20. The semiconductor device structure as claimed in claim 15 , wherein the twin boundaries have an average twin-lamella width in a range from about 4 nm to about 40 nm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jian-Hong
• Chiu Chwei-Ching
• Lee Yung-Huei
• Liao Chien-Neng
• Chueh Yu-Lun
• Chan Tsung-Cheng
• Huang Chun-Lung

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title