Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad

Patent metadata

Field	Value
Publication number	US-9760132-B2
Application number	US-201314031714-A
Country	US
Kind code	B2
Filing date	Sep 19, 2013
Priority date	Sep 19, 2013
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Stiffening is provided for an electronic package assembly having a substrate. A first electronic package, having a first function, is electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the substrate first surface. A second electronic package, having a second function, is fastened to the first substrate surface with a second conductive interconnect array. At least a pair of the first array conductors is electrically coupled to at least a pair of the second array conductors for data/signal exchange and at least a component of the first electronic package interacts with at least a component of the second package. A metallic stiffener ring is disposed about an outer periphery of at least the central area of the substrate.

First claim

What is claimed is:

1. A method of packaging an assembly of electronic devices, the method comprising:
fastening a first electronic package related to a first function electromechanically over a first surface of a substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the first surface of a substrate;
fastening a second electronic package related to a second function electromechanically over the first surface of a substrate with a second array of electrically conductive interconnects, wherein at least a pair of first conductors is electrically coupled to at least a pair of second conductors for the exchange of data or signals and wherein at least a component of the first electronic package interacts with at least a component of the second package; and
depositing a metallic stiffener ring about an outer periphery of at least the central area of the substrate.

2. The method as recited in claim 1 wherein the substrate comprises an electrically insulating material.

3. The method as recited in claim 1 wherein the first function relates to a logic operation.

4. The method as recited in claim 3 wherein the at least a component of the first electronic package comprises a processor.

5. The method as recited in claim 1 wherein the second function relates to a memory operation.

6. The method as recited in claim 1 wherein the metallic stiffener ring comprises one or more of an alloy or a metal substance.

7. The method as recited in claim 6 wherein the metal substance comprises copper.

8. The method as recited in claim 1 , further comprising, following the depositing the metal stiffener ring, disposing an electrically insulating under-fill matrix beneath at least the first component and above the substrate upper surface, wherein the under-fill matrix encapsulates the first set of interconnects, wherein a portion of the stiffener ring extends above the plane of the first surface of the substrate, and wherein the stiffening metallic ring dams a flow of an unsolidified portion of the under-fill matrix, prior to a solidification thereof, from an exclusionary area within the first surface of the substrate in which the second set of interconnects is disposed.

9. The electronic package assembly method as recited in claim 1 wherein the metallic ring is disposed about a periphery of the substrate.

10. A method of packaging an assembly of electronic devices, the method comprising:
coupling a first electronic package electromechanically over a first surface of a substrate through a first array of conductive interconnects disposed in a central area of the first surface of the substrate;
coupling a second electronic package over the first surface of the substrate with a second array of conductive interconnects, wherein at least a conductive interconnect in the first array is electrically coupled to at least a conductive interconnect in the second array, wherein at least a component of the first electronic package interacts with at least a component of the second electronic package;
depositing a metallic stiffener ring about an outer periphery of the central area of the substrate; and
disposing an electrically insulating under-fill matrix beneath the first electronic package and above the first surface of the substrate.

11. The method as recited in claim 10 , wherein the first electronic package comprises a processor.

12. The method as recited in claim 10 , wherein the second electronic package comprises a memory device.

13. The method as recited in claim 10 , wherein the metallic stiffener ring comprises one or more of an alloy or a metal substance.

14. The method as recited in claim 13 wherein the metal substance comprises copper.

15. The method as recited in claim 10 , wherein the under-fill matrix encapsulates the first array of conductive interconnects, wherein a portion of the metallic stiffener ring extends above the first surface of the substrate, and wherein the metallic stiffening ring is operable to dam a flow of an unsolidified portion of the under-fill matrix, prior to a solidification thereof, from an exclusionary area within the first surface of the substrate in which the second array of interconnects is disposed.

16. The electronic package assembly method as recited in claim 10 wherein the metallic stiffening ring is disposed about a periphery of the substrate.

17. The method as recited in claim 10 , wherein the depositing the metallic stiffener ring is performed in a metal plating process.

18. An electronic package assembly, comprising:
a substrate;
a first electronic package related to a first function and electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the first surface of the substrate;
a second electronic package related to a second function and electromechanically fastened to the first surface of the substrate with a second array of electrically conductive interconnects, wherein at least a pair of the first interconnects is electrically coupled to at least a pair of the second interconnects for the exchange of data or signals and wherein at least a component of the first electronic package is operable to interact with at least a component of the second package; and
a metallic stiffener ring disposed about an outer periphery of at least the central area of the substrate.

19. The electronic package assembly as recited in claim 18 wherein the substrate comprises an electrically insulating material.

20. The electronic package assembly as recited in claim 18 wherein the first function relates to a logic operation.

21. The electronic package assembly as recited in claim 20 wherein the at least a component of the first electronic package comprises a processor.

22. The electronic package assembly as recited in claim 18 wherein the second function relates to a memory operation.

23. The electronic package assembly as recited in claim 18 wherein the metallic stiffener ring comprises one or more of an alloy or a metal substance.

24. The electronic package assembly as recited in claim 23 wherein the metal substance comprises copper.

25. The electronic package assembly as recited in claim 18 , further comprising an electrically insulating under-fill matrix disposed above the substrate upper surface and beneath at least the first component, wherein the under-fill matrix encapsulates the first array of interconnects, wherein a portion of the stiffener ring extends above the plane of the first surface of the substrate, and wherein, prior to a solidifying set-up of the under-fill matrix, dams a flow of an unsolidified under-fill matrix from an area of the first surface of the substrate in which the second array of interconnects is disposed.

26. The electronic package assembly as recited in claim 18 wherein the metallic stiffener ring is disposed about a periphery of the substrate.

27. The electronic package assembly as recited in claim 18 wherein the first electronic package and the second electronic package comprise a package on package (PoP) configuration.

28. An electronic package product assembled by a process comprising:
fastening a first electronic package related to a first function electromechanically over a first surface of a substrate with a first plurality of interconnects, whic

Assignees

• Nvidia Corp

Inventors

• Zhang Leilei
• Boja Ron
• Yee Abraham
• Bokharey Zuhair

Classifications

• Y10T29/4913

  Assembling to base an electrical component, e.g., capacitor, etc. · CPC title

• H05K2201/2009

  Reinforced areas, e.g. for a specific part of a flexible printed circuit · CPC title

• H05K1/0271

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• G06F1/183 Primary

  Internal mounting support structures, e.g. for supporting printed circuit boards · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title