Small wafer area MEMS switch

Patent metadata

Field	Value
Publication number	US-9758366-B2
Application number	US-201514969329-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Dec 15, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

First claim

What I claim and desire to protect by Letters Patent is:

1. A small wafer area MEMS switch comprising a unitary silicon wafer having an upper and a lower surface comprising:
at said upper surface, a plurality of nine separately aligned DRIE high aspect ratio closely spaced trenches etched in said unitary silicon wafer, said trenches aligned at said upper surface to form a top appearance of a 3×3 matrix, wherein there are three columns and three row's with three entries in each said row and accordingly three entries in each column, each said trench in said first row, said second row and said third row being lined with a thermal oxide and each said trench in said first row, said second row and said third row being filled with a tungsten plug contiguous with said lined thermal oxide, there being an area on said upper wafer surface that is layered with thermal oxide, and an area on said upper wafer surface that is not layered with said thermal oxide:
a dielectric layer on said upper silicon wafer surface covering said area that is not layered with said thermal oxide;
a formed free-standing beam cantilever fixed at said upper surface of said unitary silicon wafer that is covered with said dielectric layer, said formed free-standing beam cantilever located in a hollowed etched-out volume up from said lower surface of and within said unitary silicon wafer, and said formed free-standing beam cantilever, being in vertical alignment with and normal to said area on said upper surface of said unitary silicon wafer that is covered with said dielectric layer;
said free-standing beam cantilever structure having a central portion which is a deflection electrode;
a stationary flat electrode positioned opposite to and in a plane parallel to said deflection electrode;
at least one flat drive electrode, positioned laterally and adjacent to and in a plane aligned parallel to said deflection electrode and said stationary electrode;
a gap separating a contact point on said deflection electrode from a contact point on said stationary electrode, said contact point on said deflection electrode and said contact point on said stationary electrode each being covered with an insulation material;
said deflection electrode is adapted to be electrostatically attracted toward said drive electrode with a cantilevered motion, when said drive electrode is electrically biased, with the result that said insulated contact point on said conductive layer of said deflection electrode contacts said insulated contact point on said conductive layer of said stationary electrode.

2. The small wafer area MEMS switch defined in claim 1 comprising a silicon wafer having an upper and a lower surface wherein:
said plurality of trenches comprises three separate aligned DRIE high aspect ratio closely spaced trenches in a first row, in a second row and in a third row, each said trench being lined with a thermal oxide and filled with a tungsten plug, there being an area on said upper wafer surface that is not layered with said thermal oxide, said area being layered with a dielectric layer; each of said trenches in said first row, said second row and said third row is connected by said lining of thermal oxide wherein said thermal oxide that surrounds each said trench, blends together in a space between said trenches;
said first row of trenches with said thermal oxide connecting same together and said third row of trenches with said thermal oxide connecting same together form an outer group; and said second row of trenches with said thermal oxide, located between said first row of trenches and said third row of trenches and forms an inner group;
a dielectric layer on said upper silicon wafer surface covering an area between said inner group and said outer group that is not covered with said thermal oxide;
a free-standing beam cantilever formed from said inner group fixed at said dielectric layer located within a hollowed etched out volume of said silicon wafer, extending upwardly from said lower surface of said silicon wafer, in vertical alignment with said inner group on said upper surface of said silicon wafer;
a stationary flat electrode positioned adjacent to and in a plane aligned parallel to said deflection electrode:
at least one flat drive electrode, positioned adjacent to and in a plane aligned parallel to said deflection electrode and said stationary electrode;
a gap separating a contact point on said deflection electrode from a contact point on said stationary electrode, said contact point on said deflection electrode and said contact point on said stationary electrode each being covered with an insulation material;
said deflection electrode is configured to be electrostatically attracted toward said drive electrode with a cantilevered motion, when said drive electrode is electrically biased, with the result that said insulated contact point on said conductive layer of said deflection electrode contacts said insulated contact point on said conductive layer of said stationary electrode.

3. The small wafer area MEMS switch defined in claim 2 wherein said silicon wafer includes a dual damascene interconnect wiring network as an integral part thereof.

4. The small wafer area MEMS switch defined in claim 2 wherein said silicon wafer includes a single damascene interconnect wiring network as an integral part thereof.

5. The small wafer area MEMS switch defined in claim 3 wherein said deflection electrode further includes a dielectric layer comprised of a dielectric material, and said dielectric layer of said deflection electrode is coextensive with said conductive layer on said deflection electrode.

6. The small wafer area MEMS switch defined in claim 3 wherein said contact gap is provided between diametrically opposite locations on said deflection electrode and said stationary electrode and wherein an actuation gap is provided between said deflection electrode and said drive electrode.

Assignees

• Webb Bucknell C
• IBM

Inventors

• Webb Bucknell C

Classifications

• B81B2203/0315

  Cavities · CPC title

• B81B2201/012

  characterised by the shape · CPC title

• B81B2207/07

  Interconnects · CPC title

• B81C1/00619

  Forming high aspect ratio structures having deep steep walls · CPC title

• B81C2201/0178

  Oxidation · CPC title