Thin film surface mount components

US9755609B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9755609-B2
Application numberUS-201615202814-A
CountryUS
Kind codeB2
Filing dateJul 6, 2016
Priority dateOct 16, 2009
Publication dateSep 5, 2017
Grant dateSep 5, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with internal conductive pads which are exposed to the outside of the surface mount component and electrically connected to external terminations. External terminations may include at least one layer of conductive polymer. Optional shield layers may protect the surface mount components from signal interference. A cover substrate may be formed with a plurality of conductive elements that are designed to generally align with the conductive pads such that conductive element portions are exposed in groups along surfaces of a device.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated thin film surface mount electronic component having at least two separate devices, comprising: a first thin film circuit device received on a base insulating substrate and that is positioned away from edges of the base insulating substrate so as not to be exposed to an external surface of the surface mount electronic component; an insulating layer received on said first thin film circuit device; a second thin film circuit device received on said insulating layer and that is positioned away from edges of the base insulating substrate so as not to be exposed to an external surface of the surface mount electronic component; a cover insulating substrate received on said second thin film circuit device; at least a pair of internal conductive pads, received on said base insulating substrate and said insulating layer, respectively, situated at least in part between said base insulating substrate and said cover insulating substrate, and exposed to an external surface of said surface mount electronic component; and at least a pair of electrical connectors, respectively connecting said pair of pads with said thin film circuit device. 2. An integrated thin film surface mount electronic component as in claim 1 , further including: external terminations supported on said surface mount electronic component, and directly electrically connected with said pads; and wherein said external terminations are on multiple sides of said surface mount electronic component. 3. An integrated thin film surface mount electronic component as in claim 1 , wherein said cover substrate comprises a multilayer ceramic-based component. 4. An integrated thin film surface mount electronic component as in claim 3 , wherein said cover substrate multilayer component includes at least one of internal and external anchor electrodes. 5. An integrated thin film surface mount electronic component as in claim 1 , wherein said thin film circuit device comprises one of a resistive component, a capacitor component having at least first and second conductive layers and an intermediate insulative layer, an inductive element, a multi-component circuit, and an array of components. 6. An integrated thin film surface mount electronic component as in claim 1 wherein the pair of internal conductive pads comprises: a first conductive pad and a second conductive pad with one or more electrical connectors connecting the first conductive pad and the second conductive pad to the first thin film circuit. 7. An integrated thin film surface mount electronic component as in claim 6 further comprising: a third conductive pad and a fourth conductive pad with one or more electrical connectors connecting the third conductive pad and the fourth conductive pad to the second thin film circuit. 8. An integrated thin film surface mount electronic component as in claim 7 wherein the first conductive pad and third conductive pad are separated by the insulating layer. 9. An integrated thin film surface mount electronic component as in claim 6 wherein one or more electrical connectors connect the first conductive pad and the second conductive pad to the second thin film circuit. 10. An integrated thin film surface mount electronic component as in claim 9 wherein the first conductive pad and the second conductive pad are in direct contact with the base insulating layer and the cover insulating substrate.

Assignees

Inventors

Classifications

  • H01C1/148Primary

    the terminals embracing or surrounding the resistive element (H01C1/142 takes precedence) · CPC title

  • On flat or curved insulated base, e.g., printed circuit, etc. · CPC title

  • Adding a circuit layer by thin film methods (H05K3/4647 takes precedence) · CPC title

  • by laminating two or more circuit boards (H05K3/4652 takes precedence) · CPC title

  • H03H7/17Primary

    Structural details of sub-circuits of frequency selective networks · CPC title

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Frequently asked questions

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What does patent US9755609B2 cover?
Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with in…
Who is the assignee on this patent?
Avx Corp
What technology area does this patent fall under?
Primary CPC classification H01C1/148. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).