Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact

Patent metadata

Field	Value
Publication number	US-9748375-B2
Application number	US-201615061901-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Feb 2, 2012
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

First claim

What is claimed is:

1. A semiconductor power device, comprising:
a lightly doped layer of a first conductivity type formed on top of a heavily doped layer of the first conductivity type;
a body region of a second conductivity type opposite the first conductivity type formed at an upper portion of the lightly doped layer of the first conductivity type;
a body contact region of the second conductivity type formed at an upper portion of the body region, wherein the body contact region is more heavily doped than the body region; and
one or more field effect transistor devices, each of said one or more field effect transistor devices including first and second electrically insulated gate electrodes formed in corresponding first and second trenches in the lightly doped layer and a source region of the first conductivity type extending between a sidewall of the first trench and a sidewall of the second trench, wherein each of the first and second trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer,
wherein a portion of the body region extends between the first and second trenches proximate an upper surface of the lightly doped layer;
wherein the source region of the first conductivity type includes an upper portion formed proximate the upper surface and adjacent between the first and second trenches extending along the third dimension and first and second deeper portions extending partly along the sidewalls of the first and second trenches in the first direction below the upper portion, wherein the first and second deeper portions extend in the first dimension to a depth below the bottom of the body contact region, and wherein a portion of the body contact between the first and second trenches is separated from the sidewalls of the first and second trenches by the first and second deeper portions of the source region; and
a termination area having one or more isolated termination electrodes disposed in one or more corresponding trenches formed through the body contact region and body region into the lightly doped layer of the first conductivity type and doped implant shield regions formed in the lightly doped layer of the first conductivity type adjacent bottom portions of the one or more isolated trenches extending along the third dimension, wherein each isolated termination electrode functions as a gate of a lateral MOSFET with portions of the body region between adjacent corresponding trenches functioning as a source and drain of the lateral MOSFET.

2. The device of claim 1 , wherein the source region further comprises a first and second lightly doped regions of the first conductivity type disposed below and intersecting with the first and second deeper portions of the source region, respectively, wherein the first and second lightly doped regions are less heavily doped than the upper portion and first and second deeper portions of the source region.

3. The device of claim 1 wherein each of the one or more field effect transistor devices further includes an opening formed between the first and second trenches through the upper portion of the source region and the heavily doped contact of the second conductivity type to the body region and a conductive material in the opening forming an electrical contact with a source metal that is in electrical contact with the source region.

4. The device of claim 3 , further comprising a deep contact region formed in the body region below the opening and a deep implant region of the second conductivity type formed in the lightly doped layer of a first conductivity type below and in electrical contact with the deep contact region, wherein the deep contact region is more heavily doped than the deep implant region.

5. The device of claim 1 further comprising, first and second deep shield implant regions of the second conductivity type formed in the lightly doped layer of a first conductivity type proximate the bottom of the first trench and the bottom of the second trench, respectively.

6. The device of claim 1 , wherein each of the one or more field effect transistor devices includes a thick bottom insulator formed inside and at the bottom of the first trench and the second trench, under the first gate electrode and second gate electrode.

7. The device of claim 1 , further comprising a gate contact trench formed in the lightly doped layer in communication with the first and second gate trenches, a conductive material in the gate contact trench electrically isolated from sidewalls of the gate contact trench by an insulating material, the conductive material being in electrical contact with the first and second gate electrodes and with a gate metal.

8. The device of claim 1 , wherein one or more of the termination electrodes is connected to its corresponding source.

9. The device of claim 8 , wherein a last isolated termination electrode is connected to its corresponding drain electrode to provide a channel stop.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Yilmaz Hamza
• Ng Daniel
• Calafut Daniel
• Bobde Madhur
• Bhalla Anup
• Pan Ji
• Lee Yeeheng
• Kim Jongoh

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L29/4236

  Electricity · mapped topic

• H01L29/41766

  Electricity · mapped topic

• H01L29/404

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic