Silicon interposer, semiconductor package using the same, and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9748167-B1
Application number	US-201615219230-A
Country	US
Kind code	B1
Filing date	Jul 25, 2016
Priority date	Jul 25, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A silicon interposer includes a substrate having a frontside surface and a backside surface, a first redistribution layer (RDL) structure disposed on the frontside surface, a plurality of first connecting elements disposed on the first RDL structure, a second RDL structure disposed on the backside surface, a plurality of second connecting elements disposed on the second RDL structure, and a plurality of through silicon vias in the substrate to electrically connect the first RDL structure to the second RDL structure. The first connecting elements have a first pitch. The second connecting elements have a second pitch. The second pitch is greater than the first pitch.

First claim

What is claimed is:

1. A silicon interposer, comprising:
a substrate having a frontside surface and a backside surface;
a first redistribution layer (RDL) structure disposed on the frontside surface;
a plurality of first connecting elements disposed on the first RDL structure, wherein the plurality of first connecting elements have a first pitch;
a second redistribution layer (RDL) structure disposed on the backside surface;
a plurality of second connecting elements disposed on the second RDL structure, wherein the plurality of second connecting elements have a second pitch, wherein the second pitch is greater than the first pitch;
a passivation layer on the backside surface;
a dielectric layer on the passivation layer; and
a plurality of through silicon vias (TSVs) in the substrate to electrically connect the first RDL structure to the second RDL structure, wherein the passivation layer surrounds ends of the plurality of the TSVs, and wherein the ends of the TSVs are flush with a top surface of the dielectric layer, and wherein the second RDL structure is in direct contact with the plurality of TSVs, the passivation layer and the dielectric layer.

2. The silicon interposer according to claim 1 , wherein the substrate is a silicon substrate.

3. The silicon interposer according to claim 2 , wherein no active device is disposed in or on the silicon substrate.

4. The silicon interposer according to claim 1 , wherein the plurality of first connecting elements are micro bumps and the first pitch is greater than 5 um.

5. The silicon interposer according to claim 1 , wherein the plurality of second connecting elements are ball grid array (BGA) balls and the second pitch is greater than 50 um.

6. The silicon interposer according to claim 1 , wherein the first RDL structure comprises at least an inorganic dielectric film and a fine-pitch rewiring layer.

7. The silicon interposer according to claim 6 , wherein the inorganic dielectric film comprises silicon oxide or silicon nitride.

8. The silicon interposer according to claim 6 , wherein the fine-pitch rewiring layer comprises copper.

9. The silicon interposer according to claim 1 , wherein the second RDL structure comprises at least an organic dielectric film and a trace.

10. The silicon interposer according to claim 9 , wherein the organic dielectric film comprises benzocyclobutene (BCB) or polyimide (PI).

11. A semiconductor package, comprising:
a silicon interposer, comprising:
a substrate having a frontside surface and a backside surface;
a first redistribution layer (RDL) structure disposed on the frontside surface;
a plurality of first connecting elements disposed on the first RDL structure, wherein the plurality of first connecting elements have a first pitch;
a second redistribution layer (RDL) structure disposed on the backside surface;
a plurality of second connecting elements disposed on the second RDL structure, wherein the plurality of second connecting elements have a second pitch, wherein the second pitch is greater than the first pitch;
a passivation layer on the backside surface;
a dielectric layer on the passivation layer;
a plurality of through silicon vias (TSVs) in the substrate to electrically connect the first RDL structure to the second RDL structure, wherein the passivation layer surrounds ends of the plurality of the TSVs, and wherein the ends of the TSVs are flush with a top surface of the dielectric layer, and wherein the second RDL structure is in direct contact with the plurality of TSVs, the passivation layer and the dielectric layer; and
a first semiconductor die mounted on the first RDL structure through the plurality of first connecting elements.

12. The semiconductor package according to claim 11 , wherein the first semiconductor die is a flipped chip with its active surface facing the first RDL structure.

13. The semiconductor package according to claim 12 further comprising a second semiconductor die mounted on the first RDL structure adjacent to the first semiconductor die.

14. The semiconductor package according to claim 13 , wherein the first semiconductor die comprises a central processing unit (CPU) and the second semiconductor die comprises a dynamic random access memory (DRAM).

15. The semiconductor package according to claim 11 , wherein the substrate is a silicon substrate.

16. The semiconductor package according to claim 15 , wherein no active device is disposed in or on the silicon substrate.

17. The semiconductor package according to claim 11 , wherein the plurality of first connecting elements are micro bumps and the first pitch is greater than 5 um.

18. The semiconductor package according to claim 11 , wherein the plurality of second connecting elements are ball grid array (BGA) balls and the second pitch is greater than 50 um.

19. The semiconductor package according to claim 11 , wherein the first RDL structure comprises at least an inorganic dielectric film and a fine-pitch rewiring layer.

20. The semiconductor package according to claim 19 , wherein the inorganic dielectric film comprises silicon oxide or silicon nitride.

21. The semiconductor package according to claim 19 , wherein the fine-pitch rewiring layer comprises copper.

22. The semiconductor package according to claim 11 , wherein the second RDL structure comprises at least an organic dielectric film and a trace.

23. The semiconductor package according to claim 22 , wherein the organic dielectric film comprises benzocyclobutene (BCB) or polyimide (PI).

Assignees

• United Microelectronics Corp

Inventors

• Lin Ming-Tse

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title