Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-9548240-B2
Application number	US-201514616942-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Mar 15, 2010
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a first conductive layer;
forming a first insulating layer over the first semiconductor die and first conductive layer;
disposing an encapsulant over the first semiconductor die opposite the first insulating layer;
forming a second insulating layer over the encapsulant and first insulating layer;
removing a portion of the second insulating layer to leave a first compliant island over the first conductive layer and a second compliant island extending outside a footprint of the first semiconductor die; and
forming an interconnect structure over the first compliant island.

2. The method of claim 1 , further including:
forming an opening in the first compliant island over the first conductive layer; and
forming a second conductive layer in the opening to couple the interconnect structure to the first conductive layer.

3. The method of claim 1 , wherein the interconnect structure includes a bump.

4. The method of claim 1 , further including forming an opening in the second insulating layer over the encapsulant for stress relief.

5. The method of claim 1 , wherein the second insulating layer extends at least 20 μm outside the footprint of the first semiconductor die.

6. The method of claim 1 , wherein:
disposing the encapsulant further includes disposing the encapsulant over a second semiconductor die disposed adjacent to the first semiconductor die; and
removing the portion of the second insulating layer further includes leaving the second compliant island over the first and second semiconductor die and the encapsulant between the first and second semiconductor die.

7. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
forming a first insulating layer over a first surface of the first semiconductor die;
disposing an encapsulant over a second surface of the first semiconductor die; and
forming a compliant island over the first insulating layer.

8. The method of claim 7 , further including forming an opening in the compliant island over a conductive layer formed over the first semiconductor die.

9. The method of claim 7 , wherein forming the compliant island further includes:
forming a second insulating layer over the encapsulant and first insulating layer; and
removing a portion of the second insulating layer to leave the compliant island.

10. The method of claim 9 , further including forming an opening in the second insulating layer over the encapsulant for stress relief.

11. The method of claim 9 , wherein the second insulating layer extends beyond an edge of the first semiconductor die at least 20 μm over the encapsulant.

12. The method of claim 7 , wherein:
disposing the encapsulant further includes disposing the encapsulant over a second semiconductor die disposed adjacent to the first semiconductor die; and
forming the compliant island further includes forming the compliant island over the first and second semiconductor die and the encapsulant between the first and second semiconductor die.

13. The method of claim 12 , further including forming a plurality of interconnect structures over the compliant island.

14. A semiconductor device, comprising:
a semiconductor die including a conductive layer;
a first insulating layer formed over the semiconductor die and conductive layer;
an encapsulant disposed over the semiconductor die;
a compliant island formed over the conductive layer; and
an interconnect structure formed over the compliant island.

15. The semiconductor device of claim 14 , further including an under bump metalization (UBM) formed over the compliant island, wherein the compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM.

16. The semiconductor device of claim 14 , further including an opening formed in the compliant island over the conductive layer.

17. The semiconductor device of claim 14 , further including a second insulating layer formed over the first insulating layer and compliant island.

18. The semiconductor device of claim 14 , further including a second insulating layer formed over an interface between the semiconductor die and the encapsulant with an opening formed in the second insulating layer over the encapsulant for stress relief.

19. The semiconductor device of claim 18 , wherein the second insulating layer extends beyond an edge of the semiconductor die at least 20 μm over the encapsulant.

20. A semiconductor device, comprising:
a semiconductor die;
a compliant island formed over the semiconductor die; and
a first insulating layer including a first surface that is substantially planar over a width of the compliant island.

21. The semiconductor device of claim 20 , further including a second insulating layer formed between the semiconductor die and first insulating layer.

22. The semiconductor device of claim 20 , further including an under bump metalization (UBM) formed over the compliant island, wherein the compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM.

23. The semiconductor device of claim 20 , further including:
a conductive layer formed over the semiconductor die; and
an opening formed in the compliant island over the conductive layer.

24. The semiconductor device of claim 20 , further including:
an encapsulant deposited over the semiconductor die; and
a second insulating layer formed over an interface between the semiconductor die and the encapsulant.

25. The semiconductor device of claim 24 , wherein the second insulating layer extends beyond an edge of the semiconductor die at least 20 μm outside a footprint of the semiconductor die.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chen Kang
• Fang Jianmin
• Feng Xia

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title