Semiconductor package assembly, semiconductor package and forming method thereof

Patent metadata

Field	Value
Publication number	US-9748156-B1
Application number	US-201615180264-A
Country	US
Kind code	B1
Filing date	Jun 13, 2016
Priority date	Jun 13, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a cover having at least one corner portion;
a substrate in force communication with the cover, the substrate having at least one corner portion;
at least one semiconductor device present between the cover and the substrate; and
at least one corner stiffener present on at least one of the corner portion of the cover and the corner portion of the substrate, wherein the cover has at least one recess thereon, and the at least one corner stiffener is present in the at least one recess.

2. The semiconductor package of claim 1 , wherein a plurality of the corner stiffeners are connected to form a ring.

3. The semiconductor package of claim 1 , wherein the at least one recess is annular-shaped.

4. The semiconductor package of claim 1 , wherein the cover has a top surface distal to the substrate, and the at least one recess is formed on the top surface of the cover.

5. The semiconductor package of claim 4 , wherein the cover is a molding compound, and the at least one corner stiffener is a conductive structure present in the at least one recess of the molding compound.

6. The semiconductor package of claim 5 , wherein the conductive structure is insulated from the semiconductor device.

7. The semiconductor package of claim 1 , wherein the substrate is a coreless substrate.

8. A method of forming a semiconductor package, comprising:
forming a substrate;
disposing at least one semiconductor device on the substrate;
forming a cover on the semiconductor device; and
stiffening at least one of a corner portion of the substrate and a corner portion of the cover,
wherein the forming the cover comprises forming a molding compound on the at least one semiconductor device,
wherein the stiffening comprises forming at least one recess in the molding compound, and forming a corner stiffener in the at least one recess.

9. The method of claim 8 , wherein the forming the corner stiffener comprises:
adhering the corner stiffener to the at least one recess.

10. The method of claim 8 , wherein the forming the substrate comprises:
forming at least one dielectric layer; and
forming at least one conductive layer and at least one corner stiffener on the dielectric layer.

11. The semiconductor package of claim 1 , wherein the at least one corner stiffener is embedded in the at least one recess.

12. The semiconductor package of claim 1 , wherein the cover is a molding compound, and the at least one corner stiffener is embedded in the molding compound.

13. The semiconductor package of claim 1 , further comprising:
an adhesive between a surface of the at least one recess and the at least one corner stiffener.

14. The semiconductor package of claim 1 , wherein the at least one corner stiffener is an L-shaped structure.

15. The semiconductor package of claim 1 , wherein a plurality of the corner stiffeners are separated.

16. A semiconductor package, comprising:
a cover having at least one corner portion;
a substrate coupled to the cover, the substrate having at least one corner portion;
a semiconductor device present between the cover and the substrate; and
a corner stiffener present on each of the at least one corner portion of the cover and the at least one corner portion of the substrate,
wherein the substrate comprises a plurality of conductive layers arranged along an arrangement direction of the substrate and the cover, wherein the corner stiffener is substantially level with one of the conductive layers.

17. The semiconductor package of claim 16 , wherein a plurality of the corner stiffeners are connected to form a ring, wherein said one of the conductive layers that is substantially level with the corner stiffeners is surrounded by the ring.

18. The semiconductor package of claim 16 , wherein the corner stiffener is insulated from the conductive layers.

19. The semiconductor package of claim 16 , wherein the corner stiffener is buried in the substrate.

20. The semiconductor package of claim 16 , further comprising:
a plurality of metal connectors connecting a plurality of the substrates, wherein the semiconductor device is between the metal connectors.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Shu-Shen
• Huang Cheng-Lin
• Wang Chin-Hua
• Lee Kuang-Chun
• Lin Wen-Yi
• Yew Ming-Chih
• Chen yu-huan
• Lin Po-Yao
• Leu Shyue-Ter
• Jeng Shin-Puu

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title