Semiconductor chip arrangement and method thereof

Patent metadata

Field	Value
Publication number	US-9748102-B2
Application number	US-201615289990-A
Country	US
Kind code	B2
Filing date	Oct 11, 2016
Priority date	Oct 25, 2012
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device:
providing a semiconductor carrier comprising a doped substrate region and a device region disposed over a first side of the doped substrate region;
forming one or more electrical devices at least partially in the device region; forming a gettering region comprising hydrogen-decorated intrinsic point defect complexes in the doped substrate region of the semiconductor carrier; and
adhering a metal layer disposed directly to a second side of the doped substrate region, wherein the second side of the doped substrate region faces a direction opposite to a direction which the first side of the doped substrate region faces,
wherein the doped substrate region comprises a highly doped region and an extremely highly doped region, and wherein the gettering region is formed at least partially in at least one of the highly doped region and the extremely highly doped region.

2. The method of claim 1 , wherein the doped substrate region comprises a highly doped region and wherein the gettering region is formed at least partially in the highly doped region.

3. The method of claim 2 , wherein the highly doped region has a dopant concentration ten or more times higher than a concentration of the hydrogen-decorated intrinsic point defect complexes.

4. The method of claim 1 , wherein the extremely highly doped region is proximate to the second side of the doped substrate region.

5. The method of claim 1 , wherein the highly doped region is between the extremely highly doped region and the device region.

6. The method of claim 1 , wherein the highly doped region has a dopant carrier concentration of greater than or equal to about 10 17 cm −3 and the extremely highly doped region has a dopant carrier concentration of greater than or equal to about 10 19 cm −3 .

7. The method of claim 4 , the extremely highly doped region has a dopant carrier concentration of greater than or equal to about 4×10 19 cm −3 .

8. The method of claim 4 , the extremely highly doped region has a dopant carrier concentration of greater than or equal to about 10 20 cm −3 .

9. The method of claim 1 , wherein a concentration of the hydrogen-decorated intrinsic point defect complexes is less than about 10 17 cm −3 .

10. The method of claim 1 , wherein a concentration of the hydrogen-decorated intrinsic point defect complexes is less than about or equal to about 5×10 16 cm −3 .

11. The method of claim 1 , wherein the metal layer includes a back side metallization layer including at least one of copper or aluminum.

12. The method of claim 1 , the gettering region comprises a plurality of gettering centers, wherein a maximum density of the gettering centers is located at a depth in the doped substrate region that corresponds to greater than or equal to about 30% and less than 100% of a vertical extent of the doped substrate region, wherein the depth is measured from a second side of the doped substrate region.

13. The method of claim 12 , the depth corresponds to greater than or equal to about 50% and less than 100% of the vertical extent of the doped substrate region.

14. The method of claim 1 , wherein forming the gettering region comprises implanting ions into the doped substrate region.

15. The method of claim 1 , further comprising thinning the doped substrate region from the second side of the doped substrate region.

16. The method of claim 15 , wherein the thinning of the doped substrate region occurs before forming the gettering region.

17. The method of claim 15 , wherein the thinning of the doped substrate region occurs after forming the gettering region.

18. A method for manufacturing a semiconductor device:
providing a semiconductor carrier comprising a doped substrate region and a device region disposed over a first side of the doped substrate region;
forming one or more electrical devices at least partially in the device region; forming a gettering region comprising hydrogen-decorated intrinsic point defect complexes in the doped substrate region of the semiconductor carrier; and
adhering a metal layer disposed directly to a second side of the doped substrate region, wherein the second side of the doped substrate region faces a direction opposite to a direction which the first side of the doped substrate region faces,
wherein the doped substrate region comprises a highly doped region and wherein the gettering region is formed at least partially in the highly doped region and wherein the highly doped region has a dopant concentration higher than a concentration of the hydrogen-decorated intrinsic point defect complexes.

19. A method for manufacturing a semiconductor device:
providing a semiconductor carrier comprising a doped substrate region and a device region disposed over a first side of the doped substrate region;
forming one or more electrical devices at least partially in the device region; forming a gettering region comprising hydrogen-decorated intrinsic point defect complexes in the doped substrate region of the semiconductor carrier; and
adhering a metal layer disposed directly to a second side of the doped substrate region, wherein the second side of the doped substrate region faces a direction opposite to a direction which the first side of the doped substrate region faces,
wherein the doped substrate region comprises a highly doped region and wherein the gettering region is formed at least partially in the highly doped region and wherein the highly doped region includes a dopant carrier concentration greater than about 10 17 cm −3 .

Assignees

• Infineon Technologies Ag

Inventors

• Laven Johannes
• Schulze Hans-Joachim

Classifications

• H10P36/03 Primary

  within silicon bodies · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W76/48

  Fillings including materials for absorbing or reacting with moisture or other undesired substances · CPC title